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[RFCv1,0/8] Meson-8b and Meson-gxbb USB phy code re-structure

Message ID 20210617194154.2397-1-linux.amoon@gmail.com
Headers show
Series Meson-8b and Meson-gxbb USB phy code re-structure | expand

Message

Anand Moon June 17, 2021, 7:41 p.m. UTC
On Odroid C1+ and Odroid C2 USB feature is broken
this code changes are just re-structure the code so that
proper callback function execute in proper order.

Code changes losely based on phy-meson-gxl-usb2.c

Initially if we connect USB HDD at initial boot it get detected.
but after that usb hotplug of USB HDD is broken.
I did not observe and USB debug events messages to trace the root cause.

Another issue I observed is increase of USB interrupts event
even if there is not much activity on USB ports.
I tried some clk changes but it did not workout for me.

$ cat /proc/interrupts | grep usb
 45:          0          0          0          0     GICv2  62 Level     c9000000.usb, dwc2_hsotg:usb1
 46:   17488032          0          0          0     GICv2  63 Level     c9100000.usb, dwc2_hsotg:usb2

Thanks
-Anand

Anand Moon (8):
  phy: amlogic: meson8b-usb2: Use clock bulk to get clocks for phy
  phy: amlogic: meson8b-usb2: Use phy init callback function
  phy: amlogic: meson8b-usb2: Use phy exit callback function
  phy: amlogic: meson8b-usb2: Use phy set_mode callback function
  phy: amlogic: meson8b-usb2: Reorder phy poweroff callback function
  phy: amlogic: meson8b-usb2: Use phy reset callback function
  phy: amlogic: meson8b-usb2: Power off the PHY by putting it into reset
    mode.
  phy: amlogic: meson8b-usb2: don't log an error on -EPROBE_DEFER

 drivers/phy/amlogic/phy-meson8b-usb2.c | 159 +++++++++++++++++--------
 1 file changed, 109 insertions(+), 50 deletions(-)

Comments

Martin Blumenstingl June 17, 2021, 10:11 p.m. UTC | #1
Hi Anand,

On Thu, Jun 17, 2021 at 9:42 PM Anand Moon <linux.amoon@gmail.com> wrote:
>
> On Odroid C1+ and Odroid C2 USB feature is broken
with "broken" you mean the hotplug and IRQ issues you describe below?
I think that these are not PHY related but rather a problem with the
dwc2 IP/driver

> this code changes are just re-structure the code so that
> proper callback function execute in proper order.
>
> Code changes losely based on phy-meson-gxl-usb2.c
there's a big difference between the Meson8 and GXL drivers:
GXL requires changing some of the PHY registers at runtime based on
the mode (host/peripheral).
The Meson8 PHY however (as far as I can tell from the 3.10 and 3.14
kernels) don't require any runtime changes based on the mode.

> Initially if we connect USB HDD at initial boot it get detected.
> but after that usb hotplug of USB HDD is broken.
> I did not observe and USB debug events messages to trace the root cause.
>
> Another issue I observed is increase of USB interrupts event
> even if there is not much activity on USB ports.
> I tried some clk changes but it did not workout for me.
I suggest reporting this to the dwc2 maintainers and asking for advice
on how to debug these issues.


Best regards,
Martin
Anand Moon June 18, 2021, 1:20 p.m. UTC | #2
Hi Martin,

Thanks for your review comments.
(some email id got messed up while sending these changes.)

On Fri, 18 Jun 2021 at 03:41, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
>
> Hi Anand,
>
> On Thu, Jun 17, 2021 at 9:42 PM Anand Moon <linux.amoon@gmail.com> wrote:
> >
> > On Odroid C1+ and Odroid C2 USB feature is broken
> with "broken" you mean the hotplug and IRQ issues you describe below?
> I think that these are not PHY related but rather a problem with the
> dwc2 IP/driver
>
> > this code changes are just re-structure the code so that
> > proper callback function execute in proper order.
> >
> > Code changes losely based on phy-meson-gxl-usb2.c
> there's a big difference between the Meson8 and GXL drivers:
> GXL requires changing some of the PHY registers at runtime based on
> the mode (host/peripheral).
> The Meson8 PHY however (as far as I can tell from the 3.10 and 3.14
> kernels) don't require any runtime changes based on the mode.
>
Yes I have gone through 3.10 and 3.14 kernel + u-boot source code
My intent is to simplify the code changes so that they will be
flexible to be used
in the future API.  It does not solve the problem.

> > Initially if we connect USB HDD at initial boot it get detected.
> > but after that usb hotplug of USB HDD is broken.
> > I did not observe and USB debug events messages to trace the root cause.
> >
> > Another issue I observed is increase of USB interrupts event
> > even if there is not much activity on USB ports.
> > I tried some clk changes but it did not workout for me.
> I suggest reporting this to the dwc2 maintainers and asking for advice
> on how to debug these issues.
>
Yes I have enabled the CONFIG_USB_DWC2_DEBUG
to help debug this issue but could not find much clue on
why this is happening.

I will keep debugging the DWC2 code or try to understand the missing features.

>
> Best regards,
> Martin

Thanks



-Anand
Martin Blumenstingl June 18, 2021, 8:16 p.m. UTC | #3
Hi Anand,

On Fri, Jun 18, 2021 at 3:20 PM Anand Moon <linux.amoon@gmail.com> wrote:
[...]
> (some email id got messed up while sending these changes.)
it happened to me before: don't worry, it's something that can be fixed

[...]
> > > Initially if we connect USB HDD at initial boot it get detected.
> > > but after that usb hotplug of USB HDD is broken.
> > > I did not observe and USB debug events messages to trace the root cause.
> > >
> > > Another issue I observed is increase of USB interrupts event
> > > even if there is not much activity on USB ports.
> > > I tried some clk changes but it did not workout for me.
> > I suggest reporting this to the dwc2 maintainers and asking for advice
> > on how to debug these issues.
> >
> Yes I have enabled the CONFIG_USB_DWC2_DEBUG
> to help debug this issue but could not find much clue on
> why this is happening.
I think CONFIG_USB_DWC2_DEBUG is a good starting point.
For myself I came to the conclusion that the dwc2 IP is too complex to
understand without additional information
Some additional information can be found in public datasheets of other
SoCs which are also using a dwc2 core, see for example RK3128 [0] or
RT3050 [1]
That's why my suggestion is to additionally ask the dwc2 maintainers
(which are not Cc'ed on this mail) for debugging suggestions.


Best regards,
Martin


[0] https://rockchip.fr/RK312X%20TRM/chapter-26-usb-otg-2-0.pdf
[1] http://static6.arrow.com/aropdfconversion/aa9a14376a75e7c5d6daa9f6aaed8411909d2021/rt3050_5x_v2.0_081408_0902.pdf
Anand Moon June 21, 2021, 7:21 a.m. UTC | #4
Hi Martin,

On Sat, 19 Jun 2021 at 01:47, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
>
> Hi Anand,
>
> On Fri, Jun 18, 2021 at 3:20 PM Anand Moon <linux.amoon@gmail.com> wrote:
> [...]
> > (some email id got messed up while sending these changes.)
> it happened to me before: don't worry, it's something that can be fixed
>
> [...]
> > > > Initially if we connect USB HDD at initial boot it get detected.
> > > > but after that usb hotplug of USB HDD is broken.
> > > > I did not observe and USB debug events messages to trace the root cause.
> > > >
> > > > Another issue I observed is increase of USB interrupts event
> > > > even if there is not much activity on USB ports.
> > > > I tried some clk changes but it did not workout for me.
> > > I suggest reporting this to the dwc2 maintainers and asking for advice
> > > on how to debug these issues.
> > >
> > Yes I have enabled the CONFIG_USB_DWC2_DEBUG
> > to help debug this issue but could not find much clue on
> > why this is happening.
> I think CONFIG_USB_DWC2_DEBUG is a good starting point.
> For myself I came to the conclusion that the dwc2 IP is too complex to
> understand without additional information
> Some additional information can be found in public datasheets of other
> SoCs which are also using a dwc2 core, see for example RK3128 [0] or
> RT3050 [1]
> That's why my suggestion is to additionally ask the dwc2 maintainers
> (which are not Cc'ed on this mail) for debugging suggestions.
>

Yes, I will investigate with mode debugging and Cc USB maintainers in
the next version for more details.

>
> Best regards,
> Martin
>

Thanks for these inputs.
>
> [0] https://rockchip.fr/RK312X%20TRM/chapter-26-usb-otg-2-0.pdf
> [1] http://static6.arrow.com/aropdfconversion/aa9a14376a75e7c5d6daa9f6aaed8411909d2021/rt3050_5x_v2.0_081408_0902.pdf

Thanks

-Anand