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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240531_090658_283656_D8100781 X-CRM114-Status: UNSURE ( 6.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On both QCP and CRD board currently supported upstream, the NVMe sits on the PCIe 6. Until now that has been configured in dual lane mode only. The schematics reveal that the NVMe is actually using 4 lanes. So add support for the 4-lane mode and document the compatible for it. Signed-off-by: Abel Vesa --- Abel Vesa (2): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4 phy: qcom: qmp-pcie: Add X1E80100 Gen4 4-lane mode support .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 42 ++++++++++++++++++++++ 2 files changed, 45 insertions(+) --- base-commit: 0e1980c40b6edfa68b6acf926bab22448a6e40c9 change-id: 20240531-x1e80100-phy-add-gen4x4-fa830a5505b6 Best regards,