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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f259d5b40sm7188175f8f.68.2025.02.15.04.24.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Feb 2025 04:24:12 -0800 (PST) From: Ivaylo Ivanov To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Philipp Zabel Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 0/4] phy: samsung: add Exynos2200 SNPS eUSB2 driver Date: Sat, 15 Feb 2025 14:24:05 +0200 Message-ID: <20250215122409.162810-1-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250215_042415_076397_87228654 X-CRM114-Status: GOOD ( 11.73 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hey folks, In the vendor kernel, everything is handled in a single phy driver, with helpers for functions outside it. Clocks and regulators are specified and enabled in one node, which makes it difficult to separate what clocks and regulators go where without access to schematics or TRMs. The following gates are defined for USB: CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40 CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK From what I've managed to understand, this SoC has 3 PHYs for USB: - a synopsys eusb2 phy - a synposys combophy for usbdp and superspeed - a usbcon phy, which can detach/attach pipe3 and has registers for linkctrl The approach taken here is to introduce 2 new separate drivers: one for the eusb2 and one for the usbcon. The eusb2 driver is modelled to take a phandle to the usbcon and configure/unconfigure it for the eUSB2 to become accessible and not cause a hang whenever its registers are touched. A new USBDP driver will be added later on, so that pipe3 and super-speed can be configured. Best regards, Ivaylo Ivaylo Ivanov (4): dt-bindings: phy: add samsung,exynos2200-snps-eusb2-phy schema file dt-bindings: phy: add samsung,exynos2200-usbcon-phy schema file phy: samsung: add Exynos2200 SNPS eUSB2 driver phy: samsung: add Exynos2200 usb phy controller .../samsung,exynos2200-snps-eusb2-phy.yaml | 75 ++++ .../phy/samsung,exynos2200-usbcon-phy.yaml | 70 ++++ drivers/phy/samsung/Kconfig | 26 ++ drivers/phy/samsung/Makefile | 2 + .../phy/samsung/phy-exynos2200-snps-eusb2.c | 351 ++++++++++++++++++ drivers/phy/samsung/phy-exynos2200-usbcon.c | 241 ++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 3 + 7 files changed, 768 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos2200-snps-eusb2-phy.yaml create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml create mode 100644 drivers/phy/samsung/phy-exynos2200-snps-eusb2.c create mode 100644 drivers/phy/samsung/phy-exynos2200-usbcon.c