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Thu, 15 Jun 2023 13:06:26 -0700 (PDT) Received: from stbirv-lnx-2.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id k4-20020a05620a142400b0075ceca53e84sm5721407qkj.15.2023.06.15.13.06.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Jun 2023 13:06:26 -0700 (PDT) From: Justin Chen To: linux-phy@lists.infradead.org Cc: bcm-kernel-feedback-list@broadcom.com, florian.fainelli@broadcom.com, Justin Chen , Justin Chen , Al Cooper , Vinod Koul , Kishon Vijay Abraham I , linux-kernel@vger.kernel.org (open list:BROADCOM BRCMSTB USB2 and USB3 PHY DRIVER) Subject: [PATCH 2/2] phy: usb: suppress OC condition for 7439b2 Date: Thu, 15 Jun 2023 13:06:17 -0700 Message-Id: <1686859578-45242-3-git-send-email-justin.chen@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1686859578-45242-1-git-send-email-justin.chen@broadcom.com> References: <1686859578-45242-1-git-send-email-justin.chen@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230615_130628_329625_8945FE86 X-CRM114-Status: GOOD ( 14.02 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org We hit a false positive OC for 7439b2 in DRD/device mode for the second port. So disable the OC check for this use case. Add capability to suppress OC condition for specific ports. Signed-off-by: Justin Chen Reviewed-by: Florian Fainelli --- drivers/phy/broadcom/phy-brcm-usb-init.c | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/phy/broadcom/phy-brcm-usb-init.c b/drivers/phy/broadcom/phy-brcm-usb-init.c index a1ca83308f98..39536b6d96a9 100644 --- a/drivers/phy/broadcom/phy-brcm-usb-init.c +++ b/drivers/phy/broadcom/phy-brcm-usb-init.c @@ -35,6 +35,11 @@ #define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK BIT(25) /* option */ #define USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK BIT(26) /* option */ #define USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK BIT(27) /* opt */ +#define USB_CTRL_SETUP_OC_DISABLE_PORT0_MASK BIT(28) +#define USB_CTRL_SETUP_OC_DISABLE_PORT1_MASK BIT(29) +#define USB_CTRL_SETUP_OC_DISABLE_MASK GENMASK(29, 28) /* option */ +#define USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK BIT(30) +#define USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK BIT(31) #define USB_CTRL_SETUP_OC3_DISABLE_MASK GENMASK(31, 30) /* option */ #define USB_CTRL_PLL_CTL 0x04 #define USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK BIT(27) @@ -114,6 +119,8 @@ enum { USB_CTRL_SETUP_SCB2_EN_SELECTOR, USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR, USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR, + USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR, USB_CTRL_SETUP_OC3_DISABLE_SELECTOR, USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR, USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR, @@ -190,6 +197,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { USB_CTRL_SETUP_SCB2_EN_MASK, USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, USB_CTRL_SETUP_OC3_DISABLE_MASK, 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ @@ -232,6 +241,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { USB_CTRL_SETUP_SCB2_EN_MASK, USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, USB_CTRL_SETUP_OC3_DISABLE_MASK, USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ @@ -253,6 +264,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, USB_CTRL_SETUP_OC3_DISABLE_MASK, 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, @@ -274,6 +287,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { USB_CTRL_SETUP_SCB2_EN_MASK, USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, USB_CTRL_SETUP_OC3_DISABLE_MASK, USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ @@ -295,6 +310,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { USB_CTRL_SETUP_SCB2_EN_MASK, USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, USB_CTRL_SETUP_OC3_DISABLE_MASK, 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ @@ -316,6 +333,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { USB_CTRL_SETUP_SCB2_EN_MASK, USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK, 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ + 0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK */ + 0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK */ 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */ USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ @@ -337,6 +356,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { USB_CTRL_SETUP_SCB2_EN_MASK, USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, USB_CTRL_SETUP_OC3_DISABLE_MASK, 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, @@ -358,6 +379,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { USB_CTRL_SETUP_SCB2_EN_MASK, USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK, 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, USB_CTRL_SETUP_OC3_DISABLE_MASK, USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ @@ -379,6 +402,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, USB_CTRL_SETUP_OC3_DISABLE_MASK, 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, @@ -400,6 +425,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */ USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, USB_CTRL_SETUP_OC3_DISABLE_MASK, 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, @@ -872,6 +899,13 @@ static void usb_init_common(struct brcm_usb_init_params *params) brcmusb_memc_fix(params); + /* Workaround for false positive OC for 7439b2 in DRD/Device mode */ + if ((params->family_id == 0x74390012) && + (params->supported_port_modes != USB_CTLR_MODE_HOST)) { + USB_CTRL_SET(ctrl, SETUP, OC_DISABLE_PORT1); + USB_CTRL_SET_FAMILY(params, SETUP, OC3_DISABLE_PORT1); + } + if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) { reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,