diff mbox series

[RFC,5/9] soc: imx8mm: blk-ctl: Add MIPI DPHY reset enable

Message ID 20210621072424.111733-6-jagan@amarulasolutions.com
State RFC
Headers show
Series arm64: imx8mm: Add MIPI DSI support | expand

Commit Message

Jagan Teki June 21, 2021, 7:24 a.m. UTC 
Add MIPI DPHY reset enable pin in blk-ctl driver for i.MX8MM.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/soc/imx/blk-ctl-imx8mm.c         | 4 ++++
 include/dt-bindings/power/imx8mm-power.h | 5 +++--
 2 files changed, 7 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/soc/imx/blk-ctl-imx8mm.c b/drivers/soc/imx/blk-ctl-imx8mm.c
index 5ca8d6c52917..a9d900754faf 100644
--- a/drivers/soc/imx/blk-ctl-imx8mm.c
+++ b/drivers/soc/imx/blk-ctl-imx8mm.c
@@ -25,6 +25,7 @@ 
 #define MEDIA_BLK_MIPI_CSI_I_PRESETN_SFT_EN			BIT(4)
 #define MEDIA_BLK_CAMERA_PIXEL_RESET_N_SFT_EN			BIT(3)
 #define MEDIA_BLK_CSI_BRIDGE_SFT_EN				GENMASK(2, 0)
+#define MEDIA_BLK_GPR_MIPI_M_RESETN				BIT(17)
 
 #define MEDIA_BLK_BUS_PD_MASK					BIT(12)
 #define MEDIA_BLK_MIPI_CSI_PD_MASK				GENMASK(11, 10)
@@ -41,6 +42,9 @@  static struct imx_blk_ctl_hw imx8mm_dispmix_blk_ctl_pds[] = {
 	IMX_BLK_CTL_PD("MIPI_DSI", "mipi", IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI, 0x4,
 		       MEDIA_BLK_MIPI_DSI_PD_MASK, 0, MEDIA_BLK_MIPI_DSI_I_PRESETN_SFT_EN,
 		       IMX_BLK_CTL_PD_RESET),
+	IMX_BLK_CTL_PD("DPHY", "dphy", IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY, 0x4,
+		       MEDIA_BLK_MIPI_DSI_PD_MASK, 0x8, MEDIA_BLK_GPR_MIPI_M_RESETN,
+		       IMX_BLK_CTL_PD_RESET),
 	IMX_BLK_CTL_PD("MIPI_CSI", "mipi", IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI, 0x4,
 		       MEDIA_BLK_MIPI_CSI_PD_MASK, 0,
 		       MEDIA_BLK_MIPI_CSI_I_PRESETN_SFT_EN | MEDIA_BLK_CAMERA_PIXEL_RESET_N_SFT_EN,
diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index a10266befa9c..8becb123e191 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -27,7 +27,8 @@ 
 #define IMX8MM_BLK_CTL_PD_DISPMIX_CSI_BRIDGE	0
 #define IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF		1
 #define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI	2
-#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI	3
-#define IMX8MM_BLK_CTL_PD_DISPMIX_MAX		4
+#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY	3
+#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI	4
+#define IMX8MM_BLK_CTL_PD_DISPMIX_MAX		5
 
 #endif