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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Shawn Guo , Sascha Hauer , NXP Linux Team Cc: Pengutronix Kernel Team , Fabio Estevam , devicetree@vger.kernel.org, , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, Linux Kernel Mailing List , Dong Aisheng , Jacky Bai Subject: [PATCH v9 05/12] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Date: Tue, 7 Jun 2022 14:16:18 +0300 Message-Id: <20220607111625.1845393-6-abel.vesa@nxp.com> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220607111625.1845393-1-abel.vesa@nxp.com> References: <20220607111625.1845393-1-abel.vesa@nxp.com> X-ClientProxiedBy: AM6P195CA0028.EURP195.PROD.OUTLOOK.COM (2603:10a6:209:81::41) To VI1PR04MB4688.eurprd04.prod.outlook.com (2603:10a6:803:6a::30) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4f7241e7-e54b-480b-ee0d-08da487742ee X-MS-TrafficTypeDiagnostic: DB7PR04MB4890:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: M56DO5578L8BkCoWAL5iEiPp+UQQA71c16TvDK6Nq672mKBNFi+gytHwJatrN8RO6TORV+E9V3wIJXzfSqTV2tDdiz7cXE0yd5Y23OijsX9An+HtE0chBjWoHi4gyIcGtCPzEW/iY5RfKW4krFLolaTf13am7PH5xvNpC3ZePMjTXplGTU98c3YoB0Jl/7P1vIKNZrSoQLM+HYUbM1cAWFGpVImtLLT9r3BBLmhye/dCr4IX2aq5g3j4+1snPmqPel3HBoS4uS6duEXnXvcQBKjukcCyGFpaVnqtBi6mu4e9M6+QONkEzStFwKGI6aDA2aTiJw18uS+Dhwj1+pMzSWT2xfomGBAK45+dGPEmXTYCHkZMb8nWCY/U0f+loCD9tASg3EYGK9DHtyi3wnvd2FC75xb2ViZJdy06LdNK2UCN/5XxjwmpQY5iKy54WCl9FH7G6ickZqL6oWbdFSH99Wgdpc6XQjoIvzyJRPZLb8GoaIF6/xl71nAghyBY4PDbYccJ1PJDPlsUQVLweqYS3mwIEmj7vOeUBRPYs/uoAma+5muz1uRBmXL6YD/BzLsfkMuoQHI/oYin3T76EwJ1auxKsegQtF8ypSIkUFt238qbEm30jUDTAg6QHAUQIhJj4KrT0IFk8jM9MhZtU8HmBfwC1S2VRmv0Wz370rvv0oERMWBhy+CjXAkXerEzhkQ8EgYrN3ZysAllEtDKtGN0fuPeg2NSaBc8pLyD879jpxBzCuj/XtH2WxVuwiYjF4oCA0LWTBn6zi/jSQGSZvTqEkTBQtM6zd34OMpBWbedmAYv7P/CyKU6v8axEThxdMykTSJEYFBvXWQNj/u9aEyOhCEySN+GtD0+qHuxCLYoJ5L6K2vP5xyULWuqyCBeRmvo0KpuBNESuZUa/TDLPC8s9vzP79XsCjTWit8+7nGux5h9lqzRBrTZJTPGJiDyOrAEeXPGKmrgMWb/LlSilDgzIO4ZSKuvHIQ3ov4y2/x6q9jL+ly6ZaUoxicaCtBRy2z3T3/f+3Ktc1L2NaEWsrJAUV7zj6Y/Mmlx3ffdkvzKsMaBUvgGRkVDhxcZI755+Sxj/GgXaSZaOGhaSuL9O/CAiBGmQ2O6C1ulG2WZCNISDc6yfNrEIcKVX+t+7IT30dCzNFoBPtYmReNGXaLNjlNlRLTq+0x8Ej3MvPiQkOiSukvBr0BxBF77nFCPcNQ454TYUCA1LsLYz77GQxwwd6h3mzM87IwN/V4vitL3NLpKcFvLEhKEw+5hHrob5t1iK4pkdp4FS6XlO82VjMsG2I1+gCxzuAlZhpV0Vm7inwJXSHI6x38C7CjJWnFCk19gC5oQWyw2NvrwoXysp7puIUUk9+qhcIT30wBjhtRTshCHQvE6bmB3LKWe/wsaiuTl6zRtQjyGqV8PJyZYVF/huz21HUrDEO5CLvevdqIxLNPyURwCwNsAlv6Yp7RnvjFVpXaQYeprecpMzsGYloyCcUn07DiWqKjGBWOWb+FqdwZt5Dsuo8odsFzSFi7ZEm1ZalOmqzp/YYaPn+8mbV52xLN5mdwI3WPreMQooPGhxEqi9D6zC8ZJNNoKTcoeeEWBL8a8tImz1VrIs7kS7i5d31/RX4tn4jy4AxJ/u1m2JKA1Ei3tWjU7coJjv5LJ6ytRobA7Jtm6ZWFliP1csxPL1OaCC8zH45ZqUXZWLyatV9EXIlL6sCMqtMc2zV416F5tIHUHk+N86pNnn+2vtgIeI7crzA== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4f7241e7-e54b-480b-ee0d-08da487742ee X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB4688.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2022 11:17:08.9171 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FUJfDQhjVpU1nXSOHbA4e4orFykqzO+ql2fHHoN2hIZSowRCYWmIaEHBweCn9n/4Lr/Kn6CBkl6ELPeksMu8XA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4890 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_041713_790069_E977A1A9 X-CRM114-Status: GOOD ( 14.95 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Jacky Bai The i.MX8DXL is a device targeting the automotive and industrial market segments. The flexibility of the architecture allows for use in a wide variety of general embedded applications. The chip is designed to achieve both high performance and low power consumption. The chip relies on the power efficient dual (2x) Cortex-A35 cluster. Add the reserved memory node property for dsp reserved memory, the wakeup-irq property for SCU node, the rpmsg and the cm4 rproc support. Signed-off-by: Jacky Bai Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 241 +++++++++++++++++++++ 1 file changed, 241 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi new file mode 100644 index 000000000000..6ed5f42b6f05 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &eqos; + gpio0 = &lsio_gpio0; + gpio1 = &lsio_gpio1; + gpio2 = &lsio_gpio2; + gpio3 = &lsio_gpio3; + gpio4 = &lsio_gpio4; + gpio5 = &lsio_gpio5; + gpio6 = &lsio_gpio6; + gpio7 = &lsio_gpio7; + i2c2 = &i2c2; + i2c3 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mu1 = &lsio_mu1; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 cluster with 2 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_opp_table>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a35_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", + "rx0", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 1 0 + &lsio_mu1 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8dxl-iomuxc"; + }; + + ocotp: imx8qx-ocotp { + compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; + }; + + watchdog { + compatible = "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx-sc-thermal"; + #thermal-sensor-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; + + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + /* sorted in register address */ + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" +}; + +#include "imx8dxl-ss-adma.dtsi" +#include "imx8dxl-ss-conn.dtsi" +#include "imx8dxl-ss-lsio.dtsi" +#include "imx8dxl-ss-ddr.dtsi"