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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Lynx 10G SerDes
+
+maintainers:
+  - Sean Anderson <sean.anderson@seco.com>
+
+description: |
+  These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The
+  SerDes provides up to eight lanes. Each lane may be configured individually,
+  or may be combined with adjacent lanes for a multi-lane protocol. The SerDes
+  supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and
+  others. The specific protocols supported for each lane depend on the
+  particular SoC.
+
+definitions:
+  fsl,cfg:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+    description: |
+      The configuration value to program into the field.
+
+  fsl,first-lane:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 7
+    description: |
+      The first lane in the group configured by fsl,cfg. This lane will have
+      the FIRST_LANE bit set in GCR0. The reset direction will also be set
+      based on whether this property is less than or greater than
+      fsl,last-lane.
+
+  fsl,last-lane:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 7
+    description: |
+      The last lane configured by fsl,cfg. If this property is absent,
+      then it will default to the value of fsl,first-lane.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - fsl,ls1046a-serdes
+          - fsl,ls1088a-serdes
+      - const: fsl,lynx-10g
+
+  "#clock-cells":
+    const: 1
+    description: |
+      The cell contains the index of the PLL, starting from 0. Note that when
+      assigning a rate to a PLL, the PLLs' rates are divided by 1000 to avoid
+      overflow. A rate of 5000000 corresponds to 5GHz.
+
+  "#phy-cells":
+    minimum: 1
+    maximum: 2
+    description: |
+      The cells contain the following arguments:
+      - The first lane in the group. Lanes are numbered based on the register
+        offsets, not the I/O ports. This corresponds to the letter-based ("Lane
+        A") naming scheme, and not the number-based ("Lane 0") naming scheme. On
+        most SoCs, "Lane A" is "Lane 0", but not always.
+      - Last lane. For single-lane protocols, this should be the same as the
+        first lane.
+      If no lanes in a SerDes can be grouped, then #phy-cells may be 1, and the
+      first cell will specify the only lane in the group.
+
+  clocks:
+    maxItems: 2
+    description: |
+      Clock for each PLL reference clock input.
+
+  clock-names:
+    minItems: 2
+    maxItems: 2
+    items:
+      enum:
+        - ref0
+        - ref1
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  '^pccr-':
+    type: object
+
+    description: |
+      One of the protocol configuration registers (PCCRs). These contains
+      several fields, each of which mux a particular protocol onto a particular
+      lane.
+
+    properties:
+      fsl,pccr:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          The index of the PCCR. This is the same as the register name suffix.
+          For example, a node for PCCRB would use a value of '0xb' for an
+          offset of 0x22C (0x200 + 4 * 0xb).
+
+    patternProperties:
+      '^(q?sgmii|xfi|pcie|sata)-':
+        type: object
+
+        description: |
+          A configuration field within a PCCR. Each field configures one
+          protocol controller. The value of the field determines the lanes the
+          controller is connected to, if any.
+
+        properties:
+          fsl,index:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: |
+              The index of the field. This corresponds to the suffix in the
+              documentation. For example, PEXa would be 0, PEXb 1, etc.
+              Generally, higher fields occupy lower bits.
+
+              If there are any subnodes present, they will be preferred over
+              fsl,cfg et. al.
+
+          fsl,cfg:
+            $ref: "#/definitions/fsl,cfg"
+
+          fsl,first-lane:
+            $ref: "#/definitions/fsl,first-lane"
+
+          fsl,last-lane:
+            $ref: "#/definitions/fsl,last-lane"
+
+          fsl,proto:
+            $ref: /schemas/types.yaml#/definitions/string
+            enum:
+              - sgmii
+              - sgmii25
+              - qsgmii
+              - xfi
+              - pcie
+              - sata
+            description: |
+              Indicates the basic group protocols supported by this field.
+              Individual protocols are selected by configuring the protocol
+              controller.
+
+              - sgmii: 1000BASE-X, SGMII, and 1000BASE-KX (depending on the
+                       SoC)
+              - sgmii25: 2500BASE-X, 1000BASE-X, SGMII, and 1000BASE-KX
+                         (depending on the SoC)
+              - qsgmii: QSGMII
+              - xfi: 10GBASE-R and 10GBASE-KR (depending on the SoC)
+              - pcie: PCIe
+              - sata: SATA
+
+        patternProperties:
+          '^cfg-':
+            type: object
+
+            description: |
+              A single field may have multiple values which, when programmed,
+              connect the protocol controller to different lanes. If this is the
+              case, multiple sub-nodes may be provided, each describing a
+              single muxing.
+
+            properties:
+              fsl,cfg:
+                $ref: "#/definitions/fsl,cfg"
+
+              fsl,first-lane:
+                $ref: "#/definitions/fsl,first-lane"
+
+              fsl,last-lane:
+                $ref: "#/definitions/fsl,last-lane"
+
+            required:
+              - fsl,cfg
+              - fsl,first-lane
+
+            dependencies:
+              fsl,last-lane:
+                - fsl,first-lane
+
+            additionalProperties: false
+
+        required:
+          - fsl,index
+          - fsl,proto
+
+        dependencies:
+          fsl,last-lane:
+            - fsl,first-lane
+          fsl,cfg:
+            - fsl,first-lane
+          fsl,first-lane:
+            - fsl,cfg
+
+        # I would like to require either a config subnode or the config
+        # properties (and not both), but from what I can tell that can't be
+        # expressed in json schema. In particular, it is not possible to
+        # require a pattern property.
+
+        additionalProperties: false
+
+    required:
+      - fsl,pccr
+
+    additionalProperties: false
+
+required:
+  - "#clock-cells"
+  - "#phy-cells"
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    serdes1: phy@1ea0000 {
+      #clock-cells = <1>;
+      #phy-cells = <2>;
+      compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g";
+      reg = <0x1ea0000 0x2000>;
+      clocks = <&clk_100mhz>, <&clk_156_mhz>;
+      clock-names = "ref0", "ref1";
+      assigned-clocks = <&serdes1 0>;
+      assigned-clock-rates = <5000000>;
+
+      pccr-8 {
+        fsl,pccr = <0x8>;
+
+        sgmii-0 {
+          fsl,index = <0>;
+          fsl,cfg = <0x1>;
+          fsl,first-lane = <3>;
+          fsl,proto = "sgmii";
+        };
+
+        sgmii-1 {
+          fsl,index = <1>;
+          fsl,cfg = <0x1>;
+          fsl,first-lane = <2>;
+          fsl,proto = "sgmii";
+        };
+
+        sgmii-2 {
+          fsl,index = <2>;
+          fsl,cfg = <0x1>;
+          fsl,first-lane = <1>;
+          fsl,proto = "sgmii25";
+        };
+
+        sgmii-3 {
+          fsl,index = <3>;
+          fsl,cfg = <0x1>;
+          fsl,first-lane = <0>;
+          fsl,proto = "sgmii25";
+        };
+      };
+
+      pccr-9 {
+        fsl,pccr = <0x9>;
+
+        qsgmii-0 {
+          fsl,index = <0>;
+          fsl,cfg = <0x1>;
+          fsl,first-lane = <3>;
+          fsl,proto = "qsgmii";
+        };
+
+        qsgmii-1 {
+          fsl,index = <1>;
+          fsl,proto = "qsgmii";
+
+          cfg-1 {
+            fsl,cfg = <0x1>;
+            fsl,first-lane = <2>;
+          };
+
+          cfg-2 {
+            fsl,cfg = <0x2>;
+            fsl,first-lane = <0>;
+          };
+        };
+      };
+
+      pccr-b {
+        fsl,pccr = <0xb>;
+
+        xfi-0 {
+          fsl,index = <0>;
+          fsl,cfg = <0x1>;
+          fsl,first-lane = <1>;
+          fsl,proto = "xfi";
+        };
+
+        xfi-1 {
+          fsl,index = <1>;
+          fsl,cfg = <0x1>;
+          fsl,first-lane = <0>;
+          fsl,proto = "xfi";
+        };
+      };
+    };
+...
