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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wCPo6jFQMB5IXvolGAs33GvocBeXoTUX8ScKHKCWL9iuN7P1zIcvgwaZvBDAC8rucvr349B/w3NXK48knQoblAoH8KaV0ys3fEwF24eo6U5BTCkfR2IzwbwklfPE+uscDVch3h0CEjgxfgyrxMcEmfE7aN7v1LuDSd/SOd2Gdh51JUR17Ea9V+wxkgZi2kwQ604h/M6c2P5UtFRNGKsADpUhz/p04ztcTCF2+o2eT1qilriYyUYa4O4nM51DVw1+Nvr95nQDrC2eSEztQzFKEu/um4+Kcmj7IqWbRqTWs1ECmFi4QFtWwe04KClgZNs95Uq94tJRW3rPgbAUTYIme0wI2L4EGBTtwLzMPuqe2A7blrxM9i1+W4YYzh6O0zO9TIuvYLPcQ3c2WJ8SNKkntl9BJw9t6zRYrU4xaZ9yRKpzZG3MKwSRHJR4VqdEBjJcG+XQv+1mpT+qSShvdiNsBOYYMhM7qBhIlZvlURPiMnrrjvnAwvFbnCChaJUVAQVDamcHtaSMyXCnV33U+j/wbZxdjYydfoLoccPZZRfTBuHZNqwO8kQu7OUoPV1wJvm30D818IaUCS8e+jTZP5TMVBWck+KmfpHIAUuR7grn0g1I2PmE4rttCg6Imhazw+GbvUwfqeUbnoe6CSd5xQoXMsZMcJVhRXZD3SgbKhsqWdbn/q/YvhIeQQGVmiDakb7JBnF+FRNBfb9KGiTNpt/aN7GEd/JljEC9a0bdnstOzgXXoX5R380DGnIR/+8cXPE2E+xprvuck9e8CYlM7U2CzDYNMebhF/kVjFqEcUKMmRp8RcQnSeHsvAfMR/FW28g54TvSnj3Hu1msF4lGIfdxYTEuLXEOJg8PSMeWb664phEgUGnWlrX/xlTZd86AM6vLwfkA+zGTLNS4/oHgauaFNWpRm96n4uvel8+Msr65780+/ciyaBgZQdee6SQm6Ji9/EEQlMFQq5AqUTI+IGTpvWC8pvzp3MLkBM+wo6OT5E5/REceC4cd9jViDlOskL8kpKxIZ1TcMVw5TC10u69EfRZ6J3C/U6xQusi1nzzY00msnAi+iRYRxdjCxsAXiW5pt6ZwvpugA/a4/pPwGGQiK7dBnMLEPknRedojtsXUThNAol44UcDYvvJUV5RsgAs+pWg3XoODcepZm4hRvzL+UaHAQgwb9FfhPdOJUnqMVj6NvOkm8xaAJwll7CZhO8jS9vJoTlJjV5qKBufR8ovaNntnPRc20u5amsuPYrPXLYrnOH+2RQlfcWlnR5xxJ/hxMmse4/JDFO0e3/ES6mUqyqyK4AMVmbeB5zh4R3zI7thUU661GTE8tkuYVxTYWzQqDkKic6/XCJx8RP4780grUpVwcWnQWvrafJFFiTpqyoId0lcwBGjqpNOp59fr71sFuMpzbL9wUxmCioV6NcXcfRzwbNMJ6sLUn1lA8/7sZTlkOt95Chh/L7P1uWv01pMNglP7j5fy9bm2p/vhnnm1GAZk3LdgUIS9iy7zyZ6Ca9o0WnBtpbPYT8QTgcdPAERD2m1ypWbZevYP5DiOTM3L9WQhpha5/S4PkL6O8CFGkQDA8OIPzFjuIPCPFj5yezvxYEHi3aBGAcFZbn/cQ82Riw== X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8cced2be-c3e8-4d68-1e61-08da8d2b6277 X-MS-Exchange-CrossTenant-AuthSource: DB7PR03MB4972.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2022 21:37:50.2524 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0mSRGBIg/8vob7btZDIT1jatgsLtjzyjGLkwJNSVH8MYIuOZLlNR0WaZydn6UCBtWuv3SHjrXTwdLW30tww22g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR03MB7886 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220902_143804_341696_889B1BF2 X-CRM114-Status: GOOD ( 15.41 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This adds appropriate bindings for the macs which use the SerDes. The 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is no driver for this device (and as far as I know all you can do with the 100MHz clocks is gate them), so I have chosen to model it as a single fixed clock. Note: the SerDes1 lane numbering for the LS1046A is *reversed*. This means that Lane A (what the driver thinks is lane 0) uses pins SD1_TX3_P/N. Because this will break ethernet if the serdes is not enabled, enable the serdes driver by default on Layerscape. Signed-off-by: Sean Anderson --- This depends on [1]. [1] https://lore.kernel.org/netdev/20220804194705.459670-4-sean.anderson@seco.com/ (no changes since v4) Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 112 ++++++++++++++++++ drivers/phy/freescale/Kconfig | 1 + 2 files changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 7025aad8ae89..a848556bd7db 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -10,6 +10,8 @@ /dts-v1/; +#include + #include "fsl-ls1046a.dtsi" / { @@ -26,8 +28,110 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + clocks { + clk_100mhz: clock-100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk_156mhz: clock-156mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + }; }; +&serdes1 { + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + status = "okay"; + + /* + * XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane numbers and pin + * numbers are _reversed_. In addition, the PCCR documentation is + * _inconsistent_ in its usage of these terms! + * + * PCCR "Lane 0" refers to... + * ==== ===================== + * 0 Lane A + * 2 Lane A + * 8 Lane A + * 9 Lane A + * B Lane D! + */ + serdes1_0: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* SGMII.6 */ + sgmii-0 { + fsl,pccr = <0x8>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_1: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* SGMII.5 */ + sgmii-1 { + fsl,pccr = <0x8>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_2: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* SGMII.10 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XFI.10 */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,type = ; + }; + }; + + serdes1_3: phy@3 { + #phy-cells = <0>; + reg = <3>; + + /* SGMII.9 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XGI.9 */ + xfi-9 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; +}; + + &duart0 { status = "okay"; }; @@ -140,21 +244,29 @@ ethernet@e6000 { ethernet@e8000 { phy-handle = <&sgmii_phy1>; phy-connection-type = "sgmii"; + phys = <&serdes1_1>; + phy-names = "serdes"; }; ethernet@ea000 { phy-handle = <&sgmii_phy2>; phy-connection-type = "sgmii"; + phys = <&serdes1_0>; + phy-names = "serdes"; }; ethernet@f0000 { /* 10GEC1 */ phy-handle = <&aqr106_phy>; phy-connection-type = "xgmii"; + phys = <&serdes1_3>; + phy-names = "serdes"; }; ethernet@f2000 { /* 10GEC2 */ fixed-link = <0 1 1000 0 0>; phy-connection-type = "xgmii"; + phys = <&serdes1_2>; + phy-names = "serdes"; }; mdio@fc000 { diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 6820505367cb..dcbcabe3e32f 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -52,6 +52,7 @@ config PHY_FSL_LYNX_10G tristate "Freescale Layerscale Lynx 10G SerDes support" select GENERIC_PHY select REGMAP_MMIO + default y if ARCH_LAYERSCAPE help This adds support for the Lynx "SerDes" devices found on various QorIQ SoCs. There may be up to four SerDes devices on each SoC, and each