| Message ID | 20221201174328.870152-12-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | ufs: qcom: Add HS-G4 support | expand |
On 1 December 2022 20:43:16 GMT+03:00, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: >UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init >sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance >reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > >Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> >--- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >index 75e55c4181c9..96e03d4249da 100644 >--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >@@ -935,6 +935,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { > .serdes = sm8350_ufsphy_hs_b_serdes, > .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), > }, >+ .tbls_hs_g4 = { >+ .tx = sm8350_ufsphy_g4_tx, >+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), >+ .rx = sm8350_ufsphy_g4_rx, >+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), >+ .pcs = sm8350_ufsphy_g4_pcs, >+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), >+ }, > .clk_list = sm8450_ufs_phy_clk_l, > .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), > .vreg_list = qmp_phy_vreg_l,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 75e55c4181c9..96e03d4249da 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -935,6 +935,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .serdes = sm8350_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 = { + .tx = sm8350_ufsphy_g4_tx, + .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx = sm8350_ufsphy_g4_rx, + .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs = sm8350_ufsphy_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list = sm8450_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l,
UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++ 1 file changed, 8 insertions(+)