@@ -20,6 +20,8 @@ properties:
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
- qcom,sm8350-qmp-gen3x1-pcie-phy
+ - qcom,sm8550-qmp-gen3x2-pcie-phy
+ - qcom,sm8550-qmp-gen4x2-pcie-phy
reg:
minItems: 1
@@ -43,16 +45,21 @@ properties:
maxItems: 1
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reset-names:
+ minItems: 1
items:
- const: phy
+ - const: nocsr_com
vdda-phy-supply: true
vdda-pll-supply: true
+ vdda-qref-supply: true
+
qcom,4ln-config-sel:
description: PCIe 4-lane configuration
$ref: /schemas/types.yaml#/definitions/phandle-array
@@ -113,6 +120,8 @@ allOf:
contains:
enum:
- qcom,sm8350-qmp-gen3x1-pcie-phy
+ - qcom,sm8550-qmp-gen3x2-pcie-phy
+ - qcom,sm8550-qmp-gen4x2-pcie-phy
then:
properties:
clocks:
@@ -126,6 +135,25 @@ allOf:
clock-names:
minItems: 6
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8550-qmp-gen4x2-pcie-phy
+ then:
+ properties:
+ resets:
+ minItems: 2
+ reset-names:
+ minItems: 2
+ else:
+ properties:
+ resets:
+ maxItems: 1
+ reset-names:
+ maxItems: 1
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
Document the QMP PCIe PHY compatible for SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- This patchset relies on the following patchset: https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ The v4 of this patch is: https://lore.kernel.org/all/20230119140453.3942340-2-abel.vesa@linaro.org/ Changes since v4: * constrained resets and reset-names to 1 for every other SoC Changes since v3: * increased the allowed number of resets to allow ncsr reset * added vdda-qref-supply which is used by pcie1_phy node in MTP dts * added both compatibles to the allOf:if:then clause to constrain the number of possible clocks to 5 Changes since v2: * added back the binding compatible update patch Changes since v1: * split all the offsets into separate patches, like Vinod suggested .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 30 ++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-)