| Message ID | 20230222153251.254492-6-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PCIe RC support to Qcom SDX55 SoC | expand |
On 22.02.2023 16:32, Manivannan Sadhasivam wrote: > Unit address of PCIe EP node should be 0x1c00000 as it has to match the > first address specified in the reg property. > > This also requires sorting the node in the ascending order. > > Fixes: 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller") Unsure, we aren't fixing the bindings.. > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- For the dt change: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm/boot/dts/qcom-sdx55.dtsi | 78 +++++++++++++++---------------- > 1 file changed, 39 insertions(+), 39 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi > index 93d71aff3fab..e84ca795cae6 100644 > --- a/arch/arm/boot/dts/qcom-sdx55.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi > @@ -303,6 +303,45 @@ qpic_nand: nand-controller@1b30000 { > status = "disabled"; > }; > > + pcie_ep: pcie-ep@1c00000 { > + compatible = "qcom,sdx55-pcie-ep"; > + reg = <0x01c00000 0x3000>, > + <0x40000000 0xf1d>, > + <0x40000f20 0xc8>, > + <0x40001000 0x1000>, > + <0x40200000 0x100000>, > + <0x01c03000 0x3000>; > + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", > + "mmio"; > + > + qcom,perst-regs = <&tcsr 0xb258 0xb270>; > + > + clocks = <&gcc GCC_PCIE_AUX_CLK>, > + <&gcc GCC_PCIE_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, > + <&gcc GCC_PCIE_SLEEP_CLK>, > + <&gcc GCC_PCIE_0_CLKREF_CLK>; > + clock-names = "aux", "cfg", "bus_master", "bus_slave", > + "slave_q2a", "sleep", "ref"; > + > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "global", "doorbell"; > + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; > + resets = <&gcc GCC_PCIE_BCR>; > + reset-names = "core"; > + power-domains = <&gcc PCIE_GDSC>; > + phys = <&pcie0_lane>; > + phy-names = "pciephy"; > + max-link-speed = <3>; > + num-lanes = <2>; > + > + status = "disabled"; > + }; > + > pcie0_phy: phy@1c07000 { > compatible = "qcom,sdx55-qmp-pcie-phy"; > reg = <0x01c07000 0x1c4>; > @@ -400,45 +439,6 @@ sdhc_1: mmc@8804000 { > status = "disabled"; > }; > > - pcie_ep: pcie-ep@40000000 { > - compatible = "qcom,sdx55-pcie-ep"; > - reg = <0x01c00000 0x3000>, > - <0x40000000 0xf1d>, > - <0x40000f20 0xc8>, > - <0x40001000 0x1000>, > - <0x40200000 0x100000>, > - <0x01c03000 0x3000>; > - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", > - "mmio"; > - > - qcom,perst-regs = <&tcsr 0xb258 0xb270>; > - > - clocks = <&gcc GCC_PCIE_AUX_CLK>, > - <&gcc GCC_PCIE_CFG_AHB_CLK>, > - <&gcc GCC_PCIE_MSTR_AXI_CLK>, > - <&gcc GCC_PCIE_SLV_AXI_CLK>, > - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, > - <&gcc GCC_PCIE_SLEEP_CLK>, > - <&gcc GCC_PCIE_0_CLKREF_CLK>; > - clock-names = "aux", "cfg", "bus_master", "bus_slave", > - "slave_q2a", "sleep", "ref"; > - > - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "global", "doorbell"; > - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; > - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; > - resets = <&gcc GCC_PCIE_BCR>; > - reset-names = "core"; > - power-domains = <&gcc PCIE_GDSC>; > - phys = <&pcie0_lane>; > - phy-names = "pciephy"; > - max-link-speed = <3>; > - num-lanes = <2>; > - > - status = "disabled"; > - }; > - > remoteproc_mpss: remoteproc@4080000 { > compatible = "qcom,sdx55-mpss-pas"; > reg = <0x04080000 0x4040>;
On Wed, Feb 22, 2023 at 05:02:08PM +0100, Konrad Dybcio wrote: > > > On 22.02.2023 16:32, Manivannan Sadhasivam wrote: > > Unit address of PCIe EP node should be 0x1c00000 as it has to match the > > first address specified in the reg property. > > > > This also requires sorting the node in the ascending order. > > > > Fixes: 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller") > Unsure, we aren't fixing the bindings.. > Err... will fix the tag in next version. Thanks, Mani > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > For the dt change: > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > Konrad > > arch/arm/boot/dts/qcom-sdx55.dtsi | 78 +++++++++++++++---------------- > > 1 file changed, 39 insertions(+), 39 deletions(-) > > > > diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi > > index 93d71aff3fab..e84ca795cae6 100644 > > --- a/arch/arm/boot/dts/qcom-sdx55.dtsi > > +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi > > @@ -303,6 +303,45 @@ qpic_nand: nand-controller@1b30000 { > > status = "disabled"; > > }; > > > > + pcie_ep: pcie-ep@1c00000 { > > + compatible = "qcom,sdx55-pcie-ep"; > > + reg = <0x01c00000 0x3000>, > > + <0x40000000 0xf1d>, > > + <0x40000f20 0xc8>, > > + <0x40001000 0x1000>, > > + <0x40200000 0x100000>, > > + <0x01c03000 0x3000>; > > + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", > > + "mmio"; > > + > > + qcom,perst-regs = <&tcsr 0xb258 0xb270>; > > + > > + clocks = <&gcc GCC_PCIE_AUX_CLK>, > > + <&gcc GCC_PCIE_CFG_AHB_CLK>, > > + <&gcc GCC_PCIE_MSTR_AXI_CLK>, > > + <&gcc GCC_PCIE_SLV_AXI_CLK>, > > + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, > > + <&gcc GCC_PCIE_SLEEP_CLK>, > > + <&gcc GCC_PCIE_0_CLKREF_CLK>; > > + clock-names = "aux", "cfg", "bus_master", "bus_slave", > > + "slave_q2a", "sleep", "ref"; > > + > > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "global", "doorbell"; > > + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; > > + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; > > + resets = <&gcc GCC_PCIE_BCR>; > > + reset-names = "core"; > > + power-domains = <&gcc PCIE_GDSC>; > > + phys = <&pcie0_lane>; > > + phy-names = "pciephy"; > > + max-link-speed = <3>; > > + num-lanes = <2>; > > + > > + status = "disabled"; > > + }; > > + > > pcie0_phy: phy@1c07000 { > > compatible = "qcom,sdx55-qmp-pcie-phy"; > > reg = <0x01c07000 0x1c4>; > > @@ -400,45 +439,6 @@ sdhc_1: mmc@8804000 { > > status = "disabled"; > > }; > > > > - pcie_ep: pcie-ep@40000000 { > > - compatible = "qcom,sdx55-pcie-ep"; > > - reg = <0x01c00000 0x3000>, > > - <0x40000000 0xf1d>, > > - <0x40000f20 0xc8>, > > - <0x40001000 0x1000>, > > - <0x40200000 0x100000>, > > - <0x01c03000 0x3000>; > > - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", > > - "mmio"; > > - > > - qcom,perst-regs = <&tcsr 0xb258 0xb270>; > > - > > - clocks = <&gcc GCC_PCIE_AUX_CLK>, > > - <&gcc GCC_PCIE_CFG_AHB_CLK>, > > - <&gcc GCC_PCIE_MSTR_AXI_CLK>, > > - <&gcc GCC_PCIE_SLV_AXI_CLK>, > > - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, > > - <&gcc GCC_PCIE_SLEEP_CLK>, > > - <&gcc GCC_PCIE_0_CLKREF_CLK>; > > - clock-names = "aux", "cfg", "bus_master", "bus_slave", > > - "slave_q2a", "sleep", "ref"; > > - > > - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > > - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; > > - interrupt-names = "global", "doorbell"; > > - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; > > - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; > > - resets = <&gcc GCC_PCIE_BCR>; > > - reset-names = "core"; > > - power-domains = <&gcc PCIE_GDSC>; > > - phys = <&pcie0_lane>; > > - phy-names = "pciephy"; > > - max-link-speed = <3>; > > - num-lanes = <2>; > > - > > - status = "disabled"; > > - }; > > - > > remoteproc_mpss: remoteproc@4080000 { > > compatible = "qcom,sdx55-mpss-pas"; > > reg = <0x04080000 0x4040>;
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 93d71aff3fab..e84ca795cae6 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -303,6 +303,45 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; @@ -400,45 +439,6 @@ sdhc_1: mmc@8804000 { status = "disabled"; }; - pcie_ep: pcie-ep@40000000 { - compatible = "qcom,sdx55-pcie-ep"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, - <0x40200000 0x100000>, - <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio"; - - qcom,perst-regs = <&tcsr 0xb258 0xb270>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; - - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global", "doorbell"; - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; - phy-names = "pciephy"; - max-link-speed = <3>; - num-lanes = <2>; - - status = "disabled"; - }; - remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>;
Unit address of PCIe EP node should be 0x1c00000 as it has to match the first address specified in the reg property. This also requires sorting the node in the ascending order. Fixes: 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm/boot/dts/qcom-sdx55.dtsi | 78 +++++++++++++++---------------- 1 file changed, 39 insertions(+), 39 deletions(-)