| Message ID | 20230414205425.3878902-1-dmitry.baryshkov@linaro.org |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | phy: qcom-qmp-pcie: correct sm8350 PHY tables | expand |
On 14.04.2023 22:54, Dmitry Baryshkov wrote: > Correct sm8350 PCIe PHY tables according to the vendor dtsi file. > This accounts some additional differences between PHY programming on > sm8350 and sm8450. > > The name for the PCS register 0x8 is not present in the vendor kernels, > but since on other generations the register prior to POWER_STATE_CONFIG2 > is called POWER_STATE_CONFIG1, we can establish that as its name. > > Fixes: c70052739d16 ("phy: qcom-qmp-pcie: add support for sm8350 platform") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Are you referencing the entries in lahaina-2.1.dtsi? [...] > +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_pcs_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xa8), e.g. my downstream says 0x77 here > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), Konrad > +}; > + > +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_pcs_misc_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG1, 0x0f), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), > +}; > + > +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_serdes_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), > }; > > static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { > @@ -2325,15 +2349,15 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { > .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), > .rx = sm8450_qmp_gen3_pcie_rx_tbl, > .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), > - .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, > - .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), > - .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, > - .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), > + .pcs = sm8350_qmp_gen3x1_pcie_pcs_tbl, > + .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_pcs_tbl), > + .pcs_misc = sm8350_qmp_gen3x1_pcie_pcs_misc_tbl, > + .pcs_misc_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_pcs_misc_tbl), > }, > > .tbls_rc = &(const struct qmp_phy_cfg_tbls) { > - .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, > - .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), > + .serdes = sm8350_qmp_gen3x1_pcie_rc_serdes_tbl, > + .serdes_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_serdes_tbl), > .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, > .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), > }, > @@ -2369,6 +2393,8 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { > }, > > .tbls_rc = &(const struct qmp_phy_cfg_tbls) { > + .serdes = sm8350_qmp_gen3x2_pcie_rc_serdes_tbl, > + .serdes_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_serdes_tbl), > .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, > .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), > .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > index a469ae2a10a1..ea466e14ca12 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > @@ -8,6 +8,7 @@ > #define QCOM_PHY_QMP_PCS_PCIE_V5_H_ > > /* Only for QMP V5 PHY - PCS_PCIE registers */ > +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG1 0x08 > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 > #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
On Wed, 19 Apr 2023 at 13:59, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 14.04.2023 22:54, Dmitry Baryshkov wrote: > > Correct sm8350 PCIe PHY tables according to the vendor dtsi file. > > This accounts some additional differences between PHY programming on > > sm8350 and sm8450. > > > > The name for the PCS register 0x8 is not present in the vendor kernels, > > but since on other generations the register prior to POWER_STATE_CONFIG2 > > is called POWER_STATE_CONFIG1, we can establish that as its name. > > > > Fixes: c70052739d16 ("phy: qcom-qmp-pcie: add support for sm8350 platform") > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > Are you referencing the entries in lahaina-2.1.dtsi? Let me double check it. I had this patch for quite some time in my tree. > > [...] > > > +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_pcs_tbl[] = { > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xa8), > e.g. my downstream says 0x77 here > > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), > > Konrad > > > +}; > > + > > +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_pcs_misc_tbl[] = { > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG1, 0x0f), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), > > +}; > > + > > +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_serdes_tbl[] = { > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), > > }; > > > > static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { > > @@ -2325,15 +2349,15 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { > > .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), > > .rx = sm8450_qmp_gen3_pcie_rx_tbl, > > .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), > > - .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, > > - .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), > > - .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, > > - .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), > > + .pcs = sm8350_qmp_gen3x1_pcie_pcs_tbl, > > + .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_pcs_tbl), > > + .pcs_misc = sm8350_qmp_gen3x1_pcie_pcs_misc_tbl, > > + .pcs_misc_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_pcs_misc_tbl), > > }, > > > > .tbls_rc = &(const struct qmp_phy_cfg_tbls) { > > - .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, > > - .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), > > + .serdes = sm8350_qmp_gen3x1_pcie_rc_serdes_tbl, > > + .serdes_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_serdes_tbl), > > .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, > > .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), > > }, > > @@ -2369,6 +2393,8 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { > > }, > > > > .tbls_rc = &(const struct qmp_phy_cfg_tbls) { > > + .serdes = sm8350_qmp_gen3x2_pcie_rc_serdes_tbl, > > + .serdes_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_serdes_tbl), > > .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, > > .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), > > .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > > index a469ae2a10a1..ea466e14ca12 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > > @@ -8,6 +8,7 @@ > > #define QCOM_PHY_QMP_PCS_PCIE_V5_H_ > > > > /* Only for QMP V5 PHY - PCS_PCIE registers */ > > +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG1 0x08 > > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c > > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 > > #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 5182aeac43ee..cd3e031bf506 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1265,10 +1265,10 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), }; static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), }; @@ -1321,11 +1321,16 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), }; +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), +}; + static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), }; @@ -1334,6 +1339,25 @@ static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET, 0x18), +}; + +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xa8), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), +}; + +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG1, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +}; + +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), }; static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { @@ -2325,15 +2349,15 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), .rx = sm8450_qmp_gen3_pcie_rx_tbl, .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), - .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, - .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), - .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, - .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), + .pcs = sm8350_qmp_gen3x1_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc = sm8350_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_pcs_misc_tbl), }, .tbls_rc = &(const struct qmp_phy_cfg_tbls) { - .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, - .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), + .serdes = sm8350_qmp_gen3x1_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_serdes_tbl), .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), }, @@ -2369,6 +2393,8 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { }, .tbls_rc = &(const struct qmp_phy_cfg_tbls) { + .serdes = sm8350_qmp_gen3x2_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_serdes_tbl), .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h index a469ae2a10a1..ea466e14ca12 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h @@ -8,6 +8,7 @@ #define QCOM_PHY_QMP_PCS_PCIE_V5_H_ /* Only for QMP V5 PHY - PCS_PCIE registers */ +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG1 0x08 #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
Correct sm8350 PCIe PHY tables according to the vendor dtsi file. This accounts some additional differences between PHY programming on sm8350 and sm8450. The name for the PCS register 0x8 is not present in the vendor kernels, but since on other generations the register prior to POWER_STATE_CONFIG2 is called POWER_STATE_CONFIG1, we can establish that as its name. Fixes: c70052739d16 ("phy: qcom-qmp-pcie: add support for sm8350 platform") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 42 +++++++++++++++---- .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 1 + 2 files changed, 35 insertions(+), 8 deletions(-)