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Sun, 20 Aug 2023 07:20:46 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id n9-20020a2e7209000000b002b9e501a6acsm1706222ljc.3.2023.08.20.07.20.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Aug 2023 07:20:45 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v3 11/18] arm64: dts: qcom: sc7280: switch PCIe QMP PHY to new style of bindings Date: Sun, 20 Aug 2023 17:20:28 +0300 Message-Id: <20230820142035.89903-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230820142035.89903-1-dmitry.baryshkov@linaro.org> References: <20230820142035.89903-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230820_152048_211283_32FCD327 X-CRM114-Status: UNSURE ( 8.80 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 +++++++++++----------------- 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 4353f7265877..169cf38c77d3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -869,7 +869,7 @@ gcc: clock-controller@100000 { reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <&pcie1_lane>, + <0>, <&pcie1_phy>, <0>, <0>, <0>, <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", @@ -2121,7 +2121,7 @@ pcie1: pci@1c08000 { clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane>, + <&pcie1_phy>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2155,7 +2155,7 @@ pcie1: pci@1c08000 { power-domains = <&gcc GCC_PCIE_1_GDSC>; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; pinctrl-names = "default"; @@ -2171,15 +2171,22 @@ pcie1: pci@1c08000 { pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; - reg = <0 0x01c0e000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c0e000 0 0x1000>; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -2188,21 +2195,6 @@ pcie1_phy: phy@1c0e000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c0e200 { - reg = <0 0x01c0e200 0 0x170>, - <0 0x01c0e400 0 0x200>, - <0 0x01c0ea00 0 0x1f0>, - <0 0x01c0e600 0 0x170>, - <0 0x01c0e800 0 0x200>, - <0 0x01c0ee00 0 0xf4>; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - #clock-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; }; ipa: ipa@1e40000 {