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Tue, 23 Jan 2024 23:37:30 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:30 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:37 +0530 Subject: [PATCH 09/14] arm64: dts: qcom: sc8280xp: Drop PCIE_AUX_CLK from pcie_phy nodes MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-9-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy nodes. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index febf28356ff8..cc33ef47d5a7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1785,13 +1785,12 @@ pcie4_phy: phy@1c06000 { compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; reg = <0x0 0x01c06000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_4_AUX_CLK>, - <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_4_CFG_AHB_CLK>, <&gcc GCC_PCIE_4_CLKREF_CLK>, <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_4_PIPE_CLK>, <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; @@ -1883,13 +1882,12 @@ pcie3b_phy: phy@1c0e000 { compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, - <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3B_PIPE_CLK>, <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; @@ -1982,13 +1980,12 @@ pcie3a_phy: phy@1c14000 { reg = <0x0 0x01c14000 0x0 0x2000>, <0x0 0x01c16000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, - <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3A_PIPE_CLK>, <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; @@ -2082,13 +2079,12 @@ pcie2b_phy: phy@1c1e000 { compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c1e000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, - <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2B_PIPE_CLK>, <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; @@ -2181,13 +2177,12 @@ pcie2a_phy: phy@1c24000 { reg = <0x0 0x01c24000 0x0 0x2000>, <0x0 0x01c26000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, - <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2A_PIPE_CLK>, <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;