| Message ID | 20240210204606.11944-5-aford173@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | soc: imx8mp: Finish support for HDMI | expand |
On 2/10/24 21:46, Adam Ford wrote: > From: Lucas Stach <l.stach@pengutronix.de> > > The HDMI irqsteer is a secondary interrupt controller within the HDMI > subsystem that maps all HDMI peripheral IRQs into a single upstream > IRQ line. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Marek Vasut <marex@denx.de> Thanks !
On Sat, 10 Feb 2024 14:46:00 -0600 Adam Ford <aford173@gmail.com> wrote: > From: Lucas Stach <l.stach@pengutronix.de> > > The HDMI irqsteer is a secondary interrupt controller within the HDMI > subsystem that maps all HDMI peripheral IRQs into a single upstream > IRQ line. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > V2: Add my (Adam) s-o-b and re-order position under AIPS4 > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index 0730d4cf9bc4..9b8ab367d774 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -1927,6 +1927,19 @@ hdmi_blk_ctrl: blk-ctrl@32fc0000 { > "hdcp", "hrv"; > #power-domain-cells = <1>; > }; > + > + irqsteer_hdmi: interrupt-controller@32fc2000 { > + compatible = "fsl,imx-irqsteer"; > + reg = <0x32fc2000 0x44>; The last register being at offset 0x44, this should be <0x32fc2000 0x48> or even <... 0x1000> as the TRM mentions a 4 kB size. [Tested using Avnet MSC SM2S-IMX8PLUS SoM on Avnet MSC SM2-MB-EP1] Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Luca
On Wed, Feb 14, 2024 at 5:15 AM Luca Ceresoli <luca.ceresoli@bootlin.com> wrote: > > On Sat, 10 Feb 2024 14:46:00 -0600 > Adam Ford <aford173@gmail.com> wrote: > > > From: Lucas Stach <l.stach@pengutronix.de> > > > > The HDMI irqsteer is a secondary interrupt controller within the HDMI > > subsystem that maps all HDMI peripheral IRQs into a single upstream > > IRQ line. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > Signed-off-by: Adam Ford <aford173@gmail.com> > > --- > > V2: Add my (Adam) s-o-b and re-order position under AIPS4 > > --- > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > index 0730d4cf9bc4..9b8ab367d774 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > @@ -1927,6 +1927,19 @@ hdmi_blk_ctrl: blk-ctrl@32fc0000 { > > "hdcp", "hrv"; > > #power-domain-cells = <1>; > > }; > > + > > + irqsteer_hdmi: interrupt-controller@32fc2000 { > > + compatible = "fsl,imx-irqsteer"; > > + reg = <0x32fc2000 0x44>; > > The last register being at offset 0x44, this should be <0x32fc2000 > 0x48> or even <... 0x1000> as the TRM mentions a 4 kB size. I'll do 0x1000 in the next revision to match the documentation since there doesn't appear to be any overlap. adam > > [Tested using Avnet MSC SM2S-IMX8PLUS SoM on Avnet MSC SM2-MB-EP1] > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > > > Luca > > -- > Luca Ceresoli, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 0730d4cf9bc4..9b8ab367d774 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1927,6 +1927,19 @@ hdmi_blk_ctrl: blk-ctrl@32fc0000 { "hdcp", "hrv"; #power-domain-cells = <1>; }; + + irqsteer_hdmi: interrupt-controller@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x44>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "ipg"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; + }; }; pcie: pcie@33800000 {