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AJvYcCUHWWQ15MTdKOzXlRXCchZYQCQST1DsUmFoa5IthhM74ew/F7m3+HIK0hIX5uhwwE4/boUn6B2TSstPDy54JykhJcMDfwJ/PHZUAsrXkQ== X-Gm-Message-State: AOJu0YymRrWkGvVMggGnNO0S04cCp/suL4qyL6kjCblO/vt1WMdnPZyp rH/WpEY00eVKaC9BGOuzVqOkJkmg5U/464efzDD+JJJcrBaylaPkYvVO9dtSMm3haAxr X-Google-Smtp-Source: AGHT+IGThGbZu2ZzIC/n4MZYA5OnZJb7hsEPXN8KiMr5hmglfpCIMmZO1Irlp/eAHem49FGv4ww+5A== X-Received: by 2002:a0c:e2c1:0:b0:68f:3126:a395 with SMTP id t1-20020a0ce2c1000000b0068f3126a395mr3046408qvl.31.1709071510382; Tue, 27 Feb 2024 14:05:10 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:9ee3:b2ab:6ca:180d]) by smtp.gmail.com with ESMTPSA id c12-20020a0ce14c000000b0068fc55bcf6asm4569556qvl.119.2024.02.27.14.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 14:05:10 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Cc: aford@beaconembedded.com, Lucas Stach , Adam Ford , Marek Vasut , Luca Ceresoli , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V7 5/6] arm64: dts: imx8mp: add HDMI display pipeline Date: Tue, 27 Feb 2024 16:04:39 -0600 Message-ID: <20240227220444.77566-6-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227220444.77566-1-aford173@gmail.com> References: <20240227220444.77566-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240227_140513_628272_4F65F031 X-CRM114-Status: GOOD ( 11.73 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Lucas Stach This adds the DT nodes for all the peripherals that make up the HDMI display pipeline. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli Reviewed-by: Luca Ceresoli --- V7: Make PVI node disabled by default to avoid EPROBE_DEFER V6: Make LCDIF3 disabled by default V5: No change V3: Re-ordered the HDMI parts to properly come after irqstree_hdmi inside AIPS4. Change size of LCDIF3 and PVI to match TRM sizes of 4KB. V2: I took this from Lucas' original submission with the following: Removed extra clock from HDMI-TX since it is now part of the power domain Added interrupt-parent to PVI Changed the name of the HDMI tranmitter to fsl,imx8mp-hdmi-tx Added ports to HDMI-tx --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 96 +++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 18bfa7d9aa7f..e3510fef6030 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1940,6 +1940,102 @@ irqsteer_hdmi: interrupt-controller@32fc2000 { clock-names = "ipg"; power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; }; + + hdmi_pvi: display-bridge@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pvi"; + reg = <0x32fc4000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <12>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg = <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pvi>; + }; + }; + }; + }; + + lcdif3: display-controller@32fc6000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32fc6000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <8>; + clocks = <&hdmi_tx_phy>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif3_to_pvi: endpoint { + remote-endpoint = <&pvi_from_lcdif3>; + }; + }; + }; + + hdmi_tx: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi-tx"; + reg = <0x32fd8000 0x7eff>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <0>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "cec", "pix"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint = <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg = <1>; + /* Point endpoint to the HDMI connector */ + }; + }; + }; + + hdmi_tx_phy: phy@32fdff00 { + compatible = "fsl,imx8mp-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; }; pcie: pcie@33800000 {