diff mbox series

[2/5] phy: exynos5-usbdrd: convert udelay() to fsleep()

Message ID 20240507-samsung-usb-phy-fixes-v1-2-4ccba5afa7cc@linaro.org
State Accepted
Commit 27f3d3f6d87f650cc6b3ea08335dea749f1b04aa
Headers show
Series a few fixes for the Samsung USB phy driver | expand

Commit Message

André Draszik May 7, 2024, 2:14 p.m. UTC 
The timers-howto recommends using usleep_range() and friends anytime
waiting for >= ~10us is required. Doing so can help the timer subsystem
a lot to coalesce wakeups.

Additionally, fsleep() exists as a convenient wrapper so we do not have
to think about which exact sleeping function is required in which case.

Convert all udelay() calls in this driver to use fsleep() to follow the
recommendataion.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
---
 drivers/phy/samsung/phy-exynos5-usbdrd.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Peter Griffin June 12, 2024, 8:06 a.m. UTC | #1 
Hi André,

On Tue, 7 May 2024 at 15:14, André Draszik <andre.draszik@linaro.org> wrote:
>
> The timers-howto recommends using usleep_range() and friends anytime
> waiting for >= ~10us is required. Doing so can help the timer subsystem
> a lot to coalesce wakeups.
>
> Additionally, fsleep() exists as a convenient wrapper so we do not have
> to think about which exact sleeping function is required in which case.
>
> Convert all udelay() calls in this driver to use fsleep() to follow the
> recommendataion.

Nit: typo in commit message  recommendataion -> recommendation

>
> Signed-off-by: André Draszik <andre.draszik@linaro.org>
> ---

Aside from that:

Reviewed-by:  Peter Griffin <peter.griffin@linaro.org>

[..]
diff mbox series

Patch

diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 2af192c15d78..1b209ab7a268 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -448,7 +448,7 @@  static int exynos5_usbdrd_phy_init(struct phy *phy)
 
 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
 
-	udelay(10);
+	fsleep(10);
 
 	reg &= ~PHYCLKRST_PORTRESET;
 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
@@ -779,11 +779,11 @@  static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
 	writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);
 
 	/* Finish PHY reset (POR=low) */
-	udelay(10); /* required before doing POR=low */
+	fsleep(10); /* required before doing POR=low */
 	reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
 	reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST);
 	writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
-	udelay(75); /* required after POR=low for guaranteed PHY clock */
+	fsleep(75); /* required after POR=low for guaranteed PHY clock */
 
 	/* Disable single ended signal out */
 	reg = readl(regs_base + EXYNOS850_DRD_HSP);
@@ -836,7 +836,7 @@  static int exynos850_usbdrd_phy_exit(struct phy *phy)
 	reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
 	reg |= CLKRST_LINK_SW_RST;
 	writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
-	udelay(10); /* required before doing POR=low */
+	fsleep(10); /* required before doing POR=low */
 	reg &= ~CLKRST_LINK_SW_RST;
 	writel(reg, regs_base + EXYNOS850_DRD_CLKRST);