| Message ID | 20240801-phy-qcom-qmp-pcie-write-all-tbls-second-port-v2-1-6e53c701e87e@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] phy: qcom: qmp-pcie: Configure all tables on port B PHY | expand |
On Thu, Aug 01, 2024 at 06:54:53PM GMT, Abel Vesa wrote: > From: Qiang Yu <quic_qianyu@quicinc.com> > > Currently, only the RX and TX tables are written to the second PHY > (port B) when the 4-lanes mode is configured, but according to Qualcomm > internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need > to be written as well. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > Changes in v2: > - Reordered tables as Johan has suggested > - Link to v1: https://lore.kernel.org/r/20240726-phy-qcom-qmp-pcie-write-all-tbls-second-port-v1-1-751b9ee01184@linaro.org > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 01-08-24, 18:54, Abel Vesa wrote: > From: Qiang Yu <quic_qianyu@quicinc.com> > > Currently, only the RX and TX tables are written to the second PHY > (port B) when the 4-lanes mode is configured, but according to Qualcomm > internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need > to be written as well. Sorry this does not apply on phy/next please rebase and resend
On Thu, 01 Aug 2024 18:54:53 +0300, Abel Vesa wrote: > Currently, only the RX and TX tables are written to the second PHY > (port B) when the 4-lanes mode is configured, but according to Qualcomm > internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need > to be written as well. > > Applied, thanks! [1/1] phy: qcom: qmp-pcie: Configure all tables on port B PHY commit: 00c5f32283f377ec60870bccbd518d9feb7fbc52 Best regards,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 5b36cc7ac78b..c0f4bc6b8ebc 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3660,18 +3660,30 @@ static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_ { const struct qmp_phy_cfg *cfg = qmp->cfg; const struct qmp_pcie_offsets *offs = cfg->offsets; - void __iomem *tx3, *rx3, *tx4, *rx4; + void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd; + serdes = qmp->port_b + offs->serdes; tx3 = qmp->port_b + offs->tx; rx3 = qmp->port_b + offs->rx; tx4 = qmp->port_b + offs->tx2; rx4 = qmp->port_b + offs->rx2; + pcs = qmp->port_b + offs->pcs; + pcs_misc = qmp->port_b + offs->pcs_misc; + ln_shrd = qmp->port_b + offs->ln_shrd; + + qmp_configure(serdes, tbls->serdes, tbls->serdes_num); + qmp_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); qmp_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); qmp_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); qmp_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); qmp_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); + + qmp_configure(pcs, tbls->pcs, tbls->pcs_num); + qmp_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); + + qmp_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); } static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)