Message ID | 20240904-qcs8300_initial_dtsi-v1-8-d0ea9afdc007@quicinc.com |
---|---|
State | Handled Elsewhere |
Headers | show
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Wed, 04 Sep 2024 08:35:18 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4848ZH6C029773 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Sep 2024 08:35:17 GMT Received: from jingyw-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Sep 2024 01:35:09 -0700 From: Jingyi Wang <quic_jingyw@quicinc.com> Date: Wed, 4 Sep 2024 16:33:49 +0800 Subject: [PATCH 08/19] dt-bindings: qcom,pdc: document QCS8300 Power Domain Controller MIME-Version: 1.0 Message-ID: <20240904-qcs8300_initial_dtsi-v1-8-d0ea9afdc007@quicinc.com> References: <20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com> In-Reply-To: <20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com> To: Bjorn Andersson <andersson@kernel.org>, Mathieu Poirier <mathieu.poirier@linaro.org>, Rob Herring <robh@kernel.org>, "Krzysztof Kozlowski" <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, "Bartosz Golaszewski" <bartosz.golaszewski@linaro.org>, Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@kernel.org>, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, Alim Akhtar <alim.akhtar@samsung.com>, Avri Altman <avri.altman@wdc.com>, Bart Van Assche <bvanassche@acm.org>, "Andy Gross" <agross@kernel.org>, Ulf Hansson <ulf.hansson@linaro.org>, "Thomas Gleixner" <tglx@linutronix.de>, Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Joerg Roedel <joro@8bytes.org>, Konrad Dybcio <konradybcio@kernel.org>, Robert Marko <robimarko@gmail.com>, Das Srinagesh <quic_gurus@quicinc.com>, Jassi Brar <jassisinghbrar@gmail.com>, Lee Jones <lee@kernel.org>, Srinivas Kandagatla <srinivas.kandagatla@linaro.org>, Catalin Marinas <catalin.marinas@arm.com> CC: <linux-arm-msm@vger.kernel.org>, <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>, <linux-scsi@vger.kernel.org>, <linux-pm@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>, Jingyi Wang <quic_jingyw@quicinc.com> X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" <linux-phy-bounces@lists.infradead.org> Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org |
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Add initial support for QCS8300
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diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 985fa10abb99..acd6341e9f90 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,qcs8300-pdc - qcom,qdu1000-pdc - qcom,sa8775p-pdc - qcom,sc7180-pdc
Document Power Domain Controller for QCS8300. PDC is included in QCS8300 SoC. This controller acts as an interrupt controller, enabling the detection of interrupts when the GIC is non-operational. Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+)