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AJvYcCUPylTiwTeLwnLbGYoPbmIt0mB0vhacsyM0oHzs0v34k/z406ngFnZscnPpSYZpK6Plu3ahJqGormm4@lists.infradead.org, AJvYcCUzxcxMXNiJHXRjF57VpZqIfOXSh6kBdiTgCi/T5U0htXOortK/t/90k5ayVSYyl5+Ch3JFDAJ60zyUXvXvZh8=@lists.infradead.org, AJvYcCVbxECGeZpoXpNwjlv+rQ3oWogHunK9koGjP3V3Rsxw6XA7jSS44WPlIBsFqRtG4qNdVP6StYkJbK9uC+5nfhaD@lists.infradead.org X-Gm-Message-State: AOJu0Yz0WFROoi5CqLezhIhdkpdQg6Qfumf+yd/7urTpghvUbYeRZMsY uATyaAi8YIGowPA1vkRGy6VqaDGM0ZslJivr2upZRkcjEzBUOhIr X-Google-Smtp-Source: AGHT+IHOKv/G3fft8lrCLPkbfUGY4VYY1XzqY3QsgC+ZnNRSYHKjHGuKluxzX8c+5kAFExIe9iS23w== X-Received: by 2002:a05:6a00:2288:b0:71e:ed6:1cab with SMTP id d2e1a72fcca58-71e4c1cfc19mr2588966b3a.26.1728717584316; Sat, 12 Oct 2024 00:19:44 -0700 (PDT) Received: from localhost.localdomain ([113.30.217.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2aaba171sm3664620b3a.161.2024.10.12.00.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Oct 2024 00:19:44 -0700 (PDT) From: Anand Moon To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Philipp Zabel , linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon , Dan Carpenter Subject: [PATCH v3 2/6] phy: rockchip-pcie: Use devm_clk_get_enabled() helper Date: Sat, 12 Oct 2024 12:49:04 +0530 Message-ID: <20241012071919.3726-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241012071919.3726-1-linux.amoon@gmail.com> References: <20241012071919.3726-1-linux.amoon@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241012_001945_362873_AE532D20 X-CRM114-Status: GOOD ( 16.79 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Use devm_clk_get_enabled() instead of devm_clk_get() to make the code cleaner and avoid calling clk_disable_unprepare(), as this is exactly what this function does. Use the dev_err_probe() helper to simplify error handling during probe. Refactor the mutex handling in the rockchip_pcie_phy_init() function to improve code readability and maintainability. The goto statement has been removed, and the mutex_unlock call is now directly within the conditional block. Return the result of reset_control_assert() function, with 0 indicating success and an error code indicating failure Signed-off-by: Anand Moon --- v3: Dan Carpenter: Reported below warning. smatch warnings: drivers/phy/rockchip/phy-rockchip-pcie.c:278 rockchip_pcie_phy_init() warn: missing error code 'err' So refactor the mutex_lock/mutex_unlock and return the err code. v2: Change the subject drop: Change to use/Use v1: New patch in this series --- drivers/phy/rockchip/phy-rockchip-pcie.c | 34 +++++++----------------- 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c index 51e636a1ce33..b5b1b1a667b2 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -274,30 +274,19 @@ static int rockchip_pcie_phy_init(struct phy *phy) mutex_lock(&rk_phy->pcie_mutex); - if (rk_phy->init_cnt++) - goto err_out; - - err = clk_prepare_enable(rk_phy->clk_pciephy_ref); - if (err) { - dev_err(&phy->dev, "Fail to enable pcie ref clock.\n"); - goto err_refclk; + if (rk_phy->init_cnt++) { + mutex_unlock(&rk_phy->pcie_mutex); + return 0; } err = reset_control_assert(rk_phy->phy_rst); if (err) { dev_err(&phy->dev, "assert phy_rst err %d\n", err); - goto err_reset; + rk_phy->init_cnt--; + mutex_unlock(&rk_phy->pcie_mutex); + return err; } -err_out: - mutex_unlock(&rk_phy->pcie_mutex); - return 0; - -err_reset: - - clk_disable_unprepare(rk_phy->clk_pciephy_ref); -err_refclk: - rk_phy->init_cnt--; mutex_unlock(&rk_phy->pcie_mutex); return err; } @@ -312,8 +301,6 @@ static int rockchip_pcie_phy_exit(struct phy *phy) if (--rk_phy->init_cnt) goto err_init_cnt; - clk_disable_unprepare(rk_phy->clk_pciephy_ref); - err_init_cnt: mutex_unlock(&rk_phy->pcie_mutex); return 0; @@ -375,11 +362,10 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->phy_rst), "missing phy property for reset controller\n"); - rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk"); - if (IS_ERR(rk_phy->clk_pciephy_ref)) { - dev_err(dev, "refclk not found.\n"); - return PTR_ERR(rk_phy->clk_pciephy_ref); - } + rk_phy->clk_pciephy_ref = devm_clk_get_enabled(dev, "refclk"); + if (IS_ERR(rk_phy->clk_pciephy_ref)) + return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->clk_pciephy_ref), + "failed to get phyclk\n"); /* parse #phy-cells to see if it's legacy PHY model */ if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))