From patchwork Thu Oct 24 17:05:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cody Eksal X-Patchwork-Id: 13849491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BEDA7CE8E97 for ; Thu, 24 Oct 2024 17:21:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rw0iYSWltQVvqiqcJxBCds0jD4C0JvaRV2ZC1iCoDi0=; b=of9JEFDg5cvzyr h+KW4vzooWHIIdSpdfwTCumy1TGWPYbRGXZAehdHOwdE5FldYs3ZbKyi5GVHfTzJbVpGnlVTXUhEL yaev5Etzqn3/AwbrJGQaYeMmPh5jtnFRSgIC9tZyccxCxsqeU5oim941sWYVkMWJRAaUYh4zxwpUO cmNnft8PIt9C2PTbq1z/NkQhBGkTYveGgj3V82yObLn2r4udo5OGRjHLNKULBw4XJIU1BMjfU6yX9 vjmm9G686xtfG12m+aGbNXutWZ79e/k7oruy8ZpLqt+U/AjR0l0u/FE2fzkuVx7o1aHo3pvHVgfQf xLakHt2xcQYO8SOhpArA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t41Ww-00000001GFf-0T7q; Thu, 24 Oct 2024 17:21:50 +0000 Received: from thales.epochal.quest ([2607:5300:205:200::3a30]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t41LJ-00000001DoW-0VFo; Thu, 24 Oct 2024 17:09:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=epochal.quest; s=default; t=1729789787; bh=bHPvxwNam7d5e7DDcVYjGZMshprhb5/GH93Zen2fk8E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M/0FCt16IYLO4RCFOninr0W8AfJM7xH0LRnX26BHyHD6Z9K2LjBPjpu7rf9g+aw60 tO20zweubmEKQAFJRexz9386imzHVMLd7xzIKkdXBtiSpJcBAvKvsHL/YzCiKIeLv/ zpqy5p7VHci7nUgddWFYQ6jVDZSXhLAr0HZATdKVw6YZh34CeIf5/EzSsG2teDY+KV 1TwY/LEwTw9nQEmvEOPbJWnbo6e2fPREqRFS7fTRjgcYQSb33m3BOSdXi5tTUlf+ig 3dfQ+cCmqAbEaM1ZE3ZBHRx5MH/vOdETDQWErUy+f9wQ5yJTh2L6PZdtLdMHqYsT7U L0OOu7T6TI0Og== X-Virus-Scanned: by epochal.quest From: Cody Eksal To: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Cody Eksal , Andre Przywara , Parthiban , Yangtao Li , Florian Fainelli , Vinod Koul , Linus Walleij , Thierry Reding , Krzysztof Kozlowski , Maxime Ripard , Greg Kroah-Hartman , Yangtao Li , Viresh Kumar , Nishanth Menon , Stephen Boyd , Kishon Vijay Abraham I , "Rafael J. Wysocki" Subject: [PATCH 09/13] arm64: allwinner: a100: Add MMC related nodes Date: Thu, 24 Oct 2024 14:05:27 -0300 Message-ID: <20241024170540.2721307-10-masterr3c0rd@epochal.quest> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241024170540.2721307-1-masterr3c0rd@epochal.quest> References: <20241024170540.2721307-1-masterr3c0rd@epochal.quest> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241024_100949_393587_6FEE7657 X-CRM114-Status: UNSURE ( 7.48 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Yangtao Li The A100 has 3 MMC controllers, one of them being especially targeted to eMMC. Let's add nodes on dts. Signed-off-by: Yangtao Li Reviewed-by: Andre Przywara Signed-off-by: Cody Eksal --- .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index 0aee1b578661..6dca766ea222 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -169,12 +169,83 @@ pio: pinctrl@300b000 { interrupt-controller; #interrupt-cells = <3>; + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC0", "PC1", "PC5", "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; function = "uart0"; }; }; + mmc0: mmc@4020000 { + compatible = "allwinner,sun50i-a100-mmc"; + reg = <0x04020000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun50i-a100-mmc"; + reg = <0x04021000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun50i-a100-emmc"; + reg = <0x04022000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + uart0: serial@5000000 { compatible = "snps,dw-apb-uart"; reg = <0x05000000 0x400>;