dt-bindings: phy: Correct indentation and style in DTS example

Commit Message

Krzysztof Kozlowski Jan. 7, 2025, 12:58 p.m. UTC

DTS example in the bindings should be indented with 2- or 4-spaces and
aligned with opening '- |', so correct any differences like 3-spaces or
mixtures 2- and 4-spaces in one binding.

No functional changes here, but saves some comments during reviews of
new patches built on existing code.

Signed-off-by: Krzysztof Kozlowski <[e-mail]>
---
 .../bindings/phy/calxeda-combophy.yaml        | 10 +-
 .../bindings/phy/ti,phy-j721e-wiz.yaml        | 98 +++++++++----------
 2 files changed, 54 insertions(+), 54 deletions(-)

Patch

diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
index d05a7c793035..7d75678f2ec1 100644
--- a/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
+++ b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
@@ -43,8 +43,8 @@  additionalProperties: false
 examples:
   - |
     combophy5: combo-phy@fff5d000 {
-                   compatible = "calxeda,hb-combophy";
-                   #phy-cells = <1>;
-                   reg = <0xfff5d000 0x1000>;
-                   phydev = <31>;
-               };
+        compatible = "calxeda,hb-combophy";
+        #phy-cells = <1>;
+        reg = <0xfff5d000 0x1000>;
+        phydev = <31>;
+    };
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 3f16ff14484d..ce3071fc3553 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -201,59 +201,59 @@  examples:
     #include <dt-bindings/soc/ti,sci_pm_domain.h>
 
     wiz@5000000 {
-           compatible = "ti,j721e-wiz-16g";
-           #address-cells = <1>;
-           #size-cells = <1>;
-           power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
-           clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
-           clock-names = "fck", "core_ref_clk", "ext_ref_clk";
-           assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
-           assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
-           num-lanes = <2>;
-           #reset-cells = <1>;
-           ranges = <0x5000000 0x5000000 0x10000>;
+        compatible = "ti,j721e-wiz-16g";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+        clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+        clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+        assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
+        assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
+        num-lanes = <2>;
+        #reset-cells = <1>;
+        ranges = <0x5000000 0x5000000 0x10000>;
 
-           pll0-refclk {
-                  clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
-                  #clock-cells = <0>;
-                  assigned-clocks = <&wiz1_pll0_refclk>;
-                  assigned-clock-parents = <&k3_clks 293 13>;
-           };
+        pll0-refclk {
+            clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+            #clock-cells = <0>;
+            assigned-clocks = <&wiz1_pll0_refclk>;
+            assigned-clock-parents = <&k3_clks 293 13>;
+        };
 
-           pll1-refclk {
-                  clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
-                  #clock-cells = <0>;
-                  assigned-clocks = <&wiz1_pll1_refclk>;
-                  assigned-clock-parents = <&k3_clks 293 0>;
-           };
+        pll1-refclk {
+            clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+            #clock-cells = <0>;
+            assigned-clocks = <&wiz1_pll1_refclk>;
+            assigned-clock-parents = <&k3_clks 293 0>;
+        };
 
-           cmn-refclk-dig-div {
-                  clocks = <&wiz1_refclk_dig>;
-                  #clock-cells = <0>;
-           };
+        cmn-refclk-dig-div {
+            clocks = <&wiz1_refclk_dig>;
+            #clock-cells = <0>;
+        };
 
-           cmn-refclk1-dig-div {
-                  clocks = <&wiz1_pll1_refclk>;
-                  #clock-cells = <0>;
-           };
+        cmn-refclk1-dig-div {
+            clocks = <&wiz1_pll1_refclk>;
+            #clock-cells = <0>;
+        };
 
-           refclk-dig {
-                  clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
-                          <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
-                  #clock-cells = <0>;
-                  assigned-clocks = <&wiz0_refclk_dig>;
-                  assigned-clock-parents = <&k3_clks 292 11>;
-           };
+        refclk-dig {
+            clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
+                     <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+            #clock-cells = <0>;
+            assigned-clocks = <&wiz0_refclk_dig>;
+            assigned-clock-parents = <&k3_clks 292 11>;
+        };
 
-           serdes@5000000 {
-                  compatible = "ti,sierra-phy-t0";
-                  reg-names = "serdes";
-                  reg = <0x5000000 0x10000>;
-                  #address-cells = <1>;
-                  #size-cells = <0>;
-                  resets = <&serdes_wiz0 0>;
-                  reset-names = "sierra_reset";
-                  clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
-                  clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
-           };
+        serdes@5000000 {
+            compatible = "ti,sierra-phy-t0";
+            reg-names = "serdes";
+            reg = <0x5000000 0x10000>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            resets = <&serdes_wiz0 0>;
+            reset-names = "sierra_reset";
+            clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
+            clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+        };
     };