| Message ID | DS7PR19MB8883E7167E44F92DBC29FF3C9DCB2@DS7PR19MB8883.namprd19.prod.outlook.com |
|---|---|
| State | New |
| Headers | show |
| Series | Enable IPQ5018 PCI support | expand |
On 05/03/2025 14:41, George Moussalem wrote: > From: Sricharan Ramabadhran <quic_srichara@quicinc.com> > > From: Nitheesh Sekar <quic_nsekar@quicinc.com> Nope, that's not a correct chain. Apply it yourself and check results. > > Add support for the PCIe controller on the Qualcomm > IPQ5108 SoC to the bindings. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Also not really correct. I did not provide tag to Nitheesh patch. How the tag was added there? b4? > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > Signed-off-by: George Moussalem <george.moussalem@outlook.com> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 49 +++++++++++++++++++ > 1 file changed, 49 insertions(+) > ... > + reset-names: > + items: > + - const: pipe # PIPE reset > + - const: sleep # Sleep reset > + - const: sticky # Core sticky reset > + - const: axi_m # AXI master reset > + - const: axi_s # AXI slave reset > + - const: ahb # AHB reset > + - const: axi_m_sticky # AXI master sticky reset > + - const: axi_s_sticky # AXI slave sticky reset > + interrupts: > + minItems: 8 > + interrupt-names: > + minItems: 8 Why is this flexible? > + items: > + - const: msi0 > + - const: msi1 > + - const: msi2 > + - const: msi3 > + - const: msi4 > + - const: msi5 > + - const: msi6 > + - const: msi7 > + - const: global > + Best regards, Krzysztof
On 3/5/25 19:51, Krzysztof Kozlowski wrote: > On 05/03/2025 14:41, George Moussalem wrote: >> From: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> >> From: Nitheesh Sekar <quic_nsekar@quicinc.com> > Nope, that's not a correct chain. Apply it yourself and check results. this series is dependent on the series to add support for IPQ5332: https://lore.kernel.org/all/20250220094251.230936-1-quic_varada@quicinc.com/ which was applied to dt-bindings > >> Add support for the PCIe controller on the Qualcomm >> IPQ5108 SoC to the bindings. >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Also not really correct. I did not provide tag to Nitheesh patch. How > the tag was added there? b4? the RB tag was passed on from here: https://lore.kernel.org/all/20240830081132.4016860-3-quic_srichara@quicinc.com/ but I'll drop it as it changed quite a bit since. > >> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> Signed-off-by: George Moussalem <george.moussalem@outlook.com> >> --- >> .../devicetree/bindings/pci/qcom,pcie.yaml | 49 +++++++++++++++++++ >> 1 file changed, 49 insertions(+) >> > ... > >> + reset-names: >> + items: >> + - const: pipe # PIPE reset >> + - const: sleep # Sleep reset >> + - const: sticky # Core sticky reset >> + - const: axi_m # AXI master reset >> + - const: axi_s # AXI slave reset >> + - const: ahb # AHB reset >> + - const: axi_m_sticky # AXI master sticky reset >> + - const: axi_s_sticky # AXI slave sticky reset >> + interrupts: >> + minItems: 8 >> + interrupt-names: >> + minItems: 8 > Why is this flexible? I'll restrict it with maxItems in next version, thanks > >> + items: >> + - const: msi0 >> + - const: msi1 >> + - const: msi2 >> + - const: msi3 >> + - const: msi4 >> + - const: msi5 >> + - const: msi6 >> + - const: msi7 >> + - const: global >> + > Best regards, > Krzysztof Best regards, George
On 05/03/2025 17:41, George Moussalem wrote: > > > On 3/5/25 19:51, Krzysztof Kozlowski wrote: >> On 05/03/2025 14:41, George Moussalem wrote: >>> From: Sricharan Ramabadhran <quic_srichara@quicinc.com> >>> >>> From: Nitheesh Sekar <quic_nsekar@quicinc.com> >> Nope, that's not a correct chain. Apply it yourself and check results. > this series is dependent on the series to add support for IPQ5332: > https://lore.kernel.org/all/20250220094251.230936-1-quic_varada@quicinc.com/ > which was applied to dt-bindings >> >>> Add support for the PCIe controller on the Qualcomm >>> IPQ5108 SoC to the bindings. >>> >>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Also not really correct. I did not provide tag to Nitheesh patch. How >> the tag was added there? b4? > the RB tag was passed on from here: > https://lore.kernel.org/all/20240830081132.4016860-3-quic_srichara@quicinc.com/ > but I'll drop it as it changed quite a bit since. You linked v3, but this is v3! I think I was stating it, but just to recap: please keep versioning the patchsets, so if you ever do any change, it is next version. If you do not make changes and keep the version but send again something, then this should be RESEND PATCH. >> >>> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >>> Signed-off-by: George Moussalem <george.moussalem@outlook.com> >>> --- >>> .../devicetree/bindings/pci/qcom,pcie.yaml | 49 +++++++++++++++++++ >>> 1 file changed, 49 insertions(+) >>> >> ... >> >>> + reset-names: >>> + items: >>> + - const: pipe # PIPE reset >>> + - const: sleep # Sleep reset >>> + - const: sticky # Core sticky reset >>> + - const: axi_m # AXI master reset >>> + - const: axi_s # AXI slave reset >>> + - const: ahb # AHB reset >>> + - const: axi_m_sticky # AXI master sticky reset >>> + - const: axi_s_sticky # AXI slave sticky reset >>> + interrupts: >>> + minItems: 8 >>> + interrupt-names: >>> + minItems: 8 >> Why is this flexible? > I'll restrict it with maxItems in next version, thanks This was not in v3, so is this resend of v3 or v4? You are making this process unnecessary difficult and confusing. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 6696a36009da..3aa8121b8ae9 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -210,6 +211,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5018 - qcom,pcie-ipq9574 - qcom,pcie-sdx55 then: @@ -322,6 +324,53 @@ allOf: - const: ahb # AHB reset - const: phy_ahb # PHY AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq5018 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_bridge # AXI bridge clock + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core sticky reset + - const: axi_m # AXI master reset + - const: axi_s # AXI slave reset + - const: ahb # AHB reset + - const: axi_m_sticky # AXI master sticky reset + - const: axi_s_sticky # AXI slave sticky reset + interrupts: + minItems: 8 + interrupt-names: + minItems: 8 + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: global + - if: properties: compatible: