From patchwork Mon Aug 27 15:11:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10577273 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3FF0214BD for ; Mon, 27 Aug 2018 15:11:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3046A29CEF for ; Mon, 27 Aug 2018 15:11:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E07529D41; Mon, 27 Aug 2018 15:11:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AC01429CEF for ; Mon, 27 Aug 2018 15:11:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726988AbeH0S6U (ORCPT ); Mon, 27 Aug 2018 14:58:20 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:34746 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726920AbeH0S6U (ORCPT ); Mon, 27 Aug 2018 14:58:20 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D8ED360912; Mon, 27 Aug 2018 15:11:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1535382677; bh=IiijKWDB0SccgeffDhzuFIXgBHmxBVzU8/+FRM09hZk=; h=From:To:Cc:Subject:Date:From; b=hK8IrwjxGWFWuNK9NRmk85xSWZiENj7rMaWM6jUsxTssZAdTR9VdylMMWnjNv+BIA l/++P4Pm5MScHHqApb7C9oZQsUiNN9s9wI4JwZvvQuvPinZfi9mhhMAQzC8f9GGINp fdwUbLQogRWZzWN7kWeAVV9mojC/jmF/27xURF+o= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D3DF460769; Mon, 27 Aug 2018 15:11:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1535382676; bh=IiijKWDB0SccgeffDhzuFIXgBHmxBVzU8/+FRM09hZk=; h=From:To:Cc:Subject:Date:From; b=Dj5scnGMM40JtvQ1kFiuyQuR960nCghZIxkh8+Rcyr3doC5hVPPtsWO7AzTK6l6La PS0zOpG7uuNp02ZIxIubihlg1K+CRSrHvQiq8VZ/HwMlmaJSOV7nEFL6wId2sb5zJ6 TZrlc6MqHGL8RsjP8lsjD3ax+wtSj4dxsFdoazS8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D3DF460769 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, georgi.djakov@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, bjorn.andersson@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, vireshk@kernel.org, nm@ti.com, sboyd@kernel.org Subject: [PATCH 0/9] Add interconnect support + bindings for A630 GPU Date: Mon, 27 Aug 2018 09:11:03 -0600 Message-Id: <20180827151112.25211-1-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch series is a first stab at trying to add interconnect support for the Adreno 630 GPU in the sdm845 SOC. The most interesting thing for discussion is the OPP binding for specifying bandwidth - once that is worked out the actual code to implement it is pretty straight forward thanks to the hard work from Georgi and the PM lists. The first 5 patches are are just a sync / reminder of the still pending DT bindings and entries for the GPU itself - the interconnect folks can refer to them as a reference to see what the GPU nodes will look like but I suspect they are of more interest for the GPU. Patch 6 adds a proposed binding to specify the interconnect avg/peak BW for a given operating point. On devices that can do aggressive frequency scaling like the GPU we want to be able to set a peak bandwidth along with the frequency so that we can make sure that the bus can handle a faster GPU frequency if we scale up but also to reduce power consumption on the bus when we scale down. The proposed binding uses the form: opp-interconnect-bw- = Where 'name' is the corresponding interconnect-name of the interested path and 'avg' and 'peak' are the average and peak bandwidth values in HZ to program for the operating point. The path name is used to identify path specific settings for devices that may have multiple active interconnect paths. The next patch adds a generic OPP API to read the interconnect values given a operating point and a name. The 8th patch adds code support for an interconnect path to the for the a6xx GPU reading the bandwidth for the operating point from the OPP API. And the final patch adds the actual interconnect details the device tree specifying both the interconnect details as well as the bandwidth requirements for each of the operating points on the a630 GPU. Jordan Crouse (9): drm/msm/a6xx: rnndb updates for a6xx drm/msm/a6xx: Fix PDC register overlap drm/msm/a6xx: Rename gmu phandle to qcom,gmu dt-bindings: Document qcom,adreno-gmu arm64: dts: sdm845: Add gpu and gmu device nodes PM / OPP: dt-bindings: Add opp-interconnect-bw OPP: Add dev_pm_opp_get_interconnect_bw() drm/msm/a6xx: Add support for an interconnect path arm64: dts: Add interconnect for the GPU on SDM845 .../devicetree/bindings/display/msm/gmu.txt | 54 ++ .../devicetree/bindings/display/msm/gpu.txt | 10 +- Documentation/devicetree/bindings/opp/opp.txt | 36 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 131 ++++ drivers/gpu/drm/msm/adreno/a6xx.xml.h | 642 +++++++++++------- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 114 ++-- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 6 - drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 26 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 7 + drivers/gpu/drm/msm/msm_gpu.h | 3 + drivers/opp/of.c | 36 + include/linux/pm_opp.h | 7 + 13 files changed, 775 insertions(+), 299 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt