| Message ID | 20181204192831.12440-1-miquel.raynal@bootlin.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Bring suspend to RAM support to MVEBU SATA | expand |
On 12/4/18 12:28 PM, Miquel Raynal wrote: > Hello, > > As part of an effort to bring suspend to RAM support to Armada 3700 > SoCs (main target: ESPRESSObin), this series handles the work around > the SATA IP. > > First, a change in the libahci platform adds support for the new PHY > framework by following the phy_set_mode()/phy_power_on() > sequence. Then, the AHCI MVEBU driver is a bit updated (patch 2 & 3) > and a missing initialization is added for the A3700 in patch 4 (only > done by the Bootloader before). Missing clock support is implemented > in patch 5 to be sure the clock will be resumed before this driver > (see [1] for the series adding device links to the clock core). > > Finally, device trees are updated to reflect the hardware: the missing > PHY is added to the ESPRESSObin DT, and the clock is added to the SoC > DT (patch 6 & 7). Bindings already document the clock and the PHY so > no update is needed on this regard. Probably the best/easiest to queue this through the libata tree for 4.21. Agree?
Hi Jens, Jens Axboe <axboe@kernel.dk> wrote on Tue, 4 Dec 2018 17:11:18 -0700: > On 12/4/18 12:28 PM, Miquel Raynal wrote: > > Hello, > > > > As part of an effort to bring suspend to RAM support to Armada 3700 > > SoCs (main target: ESPRESSObin), this series handles the work around > > the SATA IP. > > > > First, a change in the libahci platform adds support for the new PHY > > framework by following the phy_set_mode()/phy_power_on() > > sequence. Then, the AHCI MVEBU driver is a bit updated (patch 2 & 3) > > and a missing initialization is added for the A3700 in patch 4 (only > > done by the Bootloader before). Missing clock support is implemented > > in patch 5 to be sure the clock will be resumed before this driver > > (see [1] for the series adding device links to the clock core). > > > > Finally, device trees are updated to reflect the hardware: the missing > > PHY is added to the ESPRESSObin DT, and the clock is added to the SoC > > DT (patch 6 & 7). Bindings already document the clock and the PHY so > > no update is needed on this regard. > > Probably the best/easiest to queue this through the libata tree for > 4.21. Agree? > It looks like this patchset got left aside for 5.0, shall I re-send? (I rebased on top of 5.0 and the series applied fine). Thanks, Miquèl
On 1/11/19 6:34 AM, Miquel Raynal wrote: > Hi Jens, > > Jens Axboe <axboe@kernel.dk> wrote on Tue, 4 Dec 2018 17:11:18 -0700: > >> On 12/4/18 12:28 PM, Miquel Raynal wrote: >>> Hello, >>> >>> As part of an effort to bring suspend to RAM support to Armada 3700 >>> SoCs (main target: ESPRESSObin), this series handles the work around >>> the SATA IP. >>> >>> First, a change in the libahci platform adds support for the new PHY >>> framework by following the phy_set_mode()/phy_power_on() >>> sequence. Then, the AHCI MVEBU driver is a bit updated (patch 2 & 3) >>> and a missing initialization is added for the A3700 in patch 4 (only >>> done by the Bootloader before). Missing clock support is implemented >>> in patch 5 to be sure the clock will be resumed before this driver >>> (see [1] for the series adding device links to the clock core). >>> >>> Finally, device trees are updated to reflect the hardware: the missing >>> PHY is added to the ESPRESSObin DT, and the clock is added to the SoC >>> DT (patch 6 & 7). Bindings already document the clock and the PHY so >>> no update is needed on this regard. >> >> Probably the best/easiest to queue this through the libata tree for >> 4.21. Agree? >> > > It looks like this patchset got left aside for 5.0, shall I re-send? (I > rebased on top of 5.0 and the series applied fine). I never got a reply to the above, so I didn't add it. I've now picked up 1-5, 6-7 should go in through someone elses tree.
Hello, As part of an effort to bring suspend to RAM support to Armada 3700 SoCs (main target: ESPRESSObin), this series handles the work around the SATA IP. First, a change in the libahci platform adds support for the new PHY framework by following the phy_set_mode()/phy_power_on() sequence. Then, the AHCI MVEBU driver is a bit updated (patch 2 & 3) and a missing initialization is added for the A3700 in patch 4 (only done by the Bootloader before). Missing clock support is implemented in patch 5 to be sure the clock will be resumed before this driver (see [1] for the series adding device links to the clock core). Finally, device trees are updated to reflect the hardware: the missing PHY is added to the ESPRESSObin DT, and the clock is added to the SoC DT (patch 6 & 7). Bindings already document the clock and the PHY so no update is needed on this regard. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-November/614527.html Thanks, Miquèl Changes since v2: ================= * Rename AHCI_HFLAG_MANAGE_PHYS -> AHCI_HFLAG_SUSPEND_PHYS to clearly state that it only has an effect at suspend/resume time. * The hflag is not passed to ahci_platform_get_resources() anymore but added manually by the users (in our case, ahci_mvebu.c) in the probe. * Refactor a bit the patch bringin S2RAM support to the ahci_mvebu driver by splitting the changes: one patch just for registers initialization, another one to make use of the above hflag. Changes since v1: ================= * The clock is automatically requested by the libahci_platform.c driver, doing it in the mvebu driver is redundant, remove the patch adding clock support as clock support already exists. * Changed authorship of patch adding a SATA enum in the PHY core. * Added Suggested-by tag to the patch fixing the SATA node scope in DT, to the patch adding PHY framework compliance to the libahci_platform driver and to the DT patch adding the SATA PHY property. * Add a flag to do not disable/enable the PHY for compatibility reasons and to avoid to break untested boards with this change. The flag is called AHCI_HFLAG_MANAGE_PHYS. * The mvebu ahci driver is edited to enable this flag only on A3700. Miquel Raynal (7): ata: libahci_platform: comply to PHY framework ata: ahci: mvebu: remove stale comment ata: ahci: mvebu: do Armada 38x configuration only on relevant SoCs ata: ahci: mvebu: add Armada 3700 initialization needed for S2RAM ata: ahci: mvebu: request PHY suspend/resume for Armada 3700 ARM64: dts: marvell: armada-37xx: declare SATA clock ARM64: dts: marvell: armada-3720-espressobin: declare SATA PHY property .../dts/marvell/armada-3720-espressobin.dts | 2 + arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + drivers/ata/ahci.h | 2 + drivers/ata/ahci_mvebu.c | 87 ++++++++++++++----- drivers/ata/libahci_platform.c | 13 +++ 5 files changed, 82 insertions(+), 23 deletions(-)