From patchwork Tue Dec 4 19:28:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10712509 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D6A9913BF for ; Tue, 4 Dec 2018 19:28:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C42342BE2E for ; Tue, 4 Dec 2018 19:28:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B0B602BDF4; Tue, 4 Dec 2018 19:28:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F1A912BDF4 for ; Tue, 4 Dec 2018 19:28:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725919AbeLDT2r (ORCPT ); Tue, 4 Dec 2018 14:28:47 -0500 Received: from mail.bootlin.com ([62.4.15.54]:47846 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725855AbeLDT2q (ORCPT ); Tue, 4 Dec 2018 14:28:46 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id A22E120A5F; Tue, 4 Dec 2018 20:28:43 +0100 (CET) Received: from localhost.localdomain (unknown [91.224.148.103]) by mail.bootlin.com (Postfix) with ESMTPSA id A7AE1207A8; Tue, 4 Dec 2018 20:28:32 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Rob Herring , Mark Rutland , Jens Axboe , Hans de Goede Cc: , , linux-ide@vger.kernel.org, linux-pm@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 0/7] Bring suspend to RAM support to MVEBU SATA Date: Tue, 4 Dec 2018 20:28:24 +0100 Message-Id: <20181204192831.12440-1-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hello, As part of an effort to bring suspend to RAM support to Armada 3700 SoCs (main target: ESPRESSObin), this series handles the work around the SATA IP. First, a change in the libahci platform adds support for the new PHY framework by following the phy_set_mode()/phy_power_on() sequence. Then, the AHCI MVEBU driver is a bit updated (patch 2 & 3) and a missing initialization is added for the A3700 in patch 4 (only done by the Bootloader before). Missing clock support is implemented in patch 5 to be sure the clock will be resumed before this driver (see [1] for the series adding device links to the clock core). Finally, device trees are updated to reflect the hardware: the missing PHY is added to the ESPRESSObin DT, and the clock is added to the SoC DT (patch 6 & 7). Bindings already document the clock and the PHY so no update is needed on this regard. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-November/614527.html Thanks, Miquèl Changes since v2: ================= * Rename AHCI_HFLAG_MANAGE_PHYS -> AHCI_HFLAG_SUSPEND_PHYS to clearly state that it only has an effect at suspend/resume time. * The hflag is not passed to ahci_platform_get_resources() anymore but added manually by the users (in our case, ahci_mvebu.c) in the probe. * Refactor a bit the patch bringin S2RAM support to the ahci_mvebu driver by splitting the changes: one patch just for registers initialization, another one to make use of the above hflag. Changes since v1: ================= * The clock is automatically requested by the libahci_platform.c driver, doing it in the mvebu driver is redundant, remove the patch adding clock support as clock support already exists. * Changed authorship of patch adding a SATA enum in the PHY core. * Added Suggested-by tag to the patch fixing the SATA node scope in DT, to the patch adding PHY framework compliance to the libahci_platform driver and to the DT patch adding the SATA PHY property. * Add a flag to do not disable/enable the PHY for compatibility reasons and to avoid to break untested boards with this change. The flag is called AHCI_HFLAG_MANAGE_PHYS. * The mvebu ahci driver is edited to enable this flag only on A3700. Miquel Raynal (7): ata: libahci_platform: comply to PHY framework ata: ahci: mvebu: remove stale comment ata: ahci: mvebu: do Armada 38x configuration only on relevant SoCs ata: ahci: mvebu: add Armada 3700 initialization needed for S2RAM ata: ahci: mvebu: request PHY suspend/resume for Armada 3700 ARM64: dts: marvell: armada-37xx: declare SATA clock ARM64: dts: marvell: armada-3720-espressobin: declare SATA PHY property .../dts/marvell/armada-3720-espressobin.dts | 2 + arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + drivers/ata/ahci.h | 2 + drivers/ata/ahci_mvebu.c | 87 ++++++++++++++----- drivers/ata/libahci_platform.c | 13 +++ 5 files changed, 82 insertions(+), 23 deletions(-)