From patchwork Tue Dec 18 18:32:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10736137 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D885B6C2 for ; Tue, 18 Dec 2018 18:32:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA3AC2ACDA for ; Tue, 18 Dec 2018 18:32:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BEC482AD9C; Tue, 18 Dec 2018 18:32:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C0B62ACDA for ; Tue, 18 Dec 2018 18:32:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727758AbeLRScs (ORCPT ); Tue, 18 Dec 2018 13:32:48 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:41728 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727479AbeLRScs (ORCPT ); Tue, 18 Dec 2018 13:32:48 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 738E0606CF; Tue, 18 Dec 2018 18:32:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157967; bh=mfrC/dck5Y3m6dfG9iC4qNDfYJvVj8GYunV7aIowih4=; h=From:To:Cc:Subject:Date:From; b=ZG0Nf5OmHhVdSdtNOmAUi0gYoDR/7D7eErQam/FIsZ2PAElhxBB+e1i30n5erDR+5 f5u0/I91SDTpiJUMi5VhbIj5iXukhFu1HiYgCCY0wzTL+ugADQP+9ed/A4eJXU8r8z XfziPMZFdBJ19EKMoXpP8+RIkgWNfQuv+YBoOSMs= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2D24D606CF; Tue, 18 Dec 2018 18:32:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157966; bh=mfrC/dck5Y3m6dfG9iC4qNDfYJvVj8GYunV7aIowih4=; h=From:To:Cc:Subject:Date:From; b=GOrCGUItYZegNip5X9CzaAe2zdoOG7Zh9wnk17x2LV1jY0BmgTldwVtV1LKAL0Lvh UZipqLjKpmuMfTXY2vmPhgmI6UY/QfH0A1qts8j03COV8GkKBgGc6rXsDwVx9auzCb pCwnSkZxfObSYds9EOz6ikb/orouKmDVS26Oy/gg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2D24D606CF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, vireshk@kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org Subject: [PATCH v7 0/6] arm64: dts: Add sdm845 GPU/GMU and SMMU Date: Tue, 18 Dec 2018 11:32:35 -0700 Message-Id: <20181218183241.12830-1-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Now that more of the sdm845 bindings are headed upstream this a refresh of of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes for the GPU/GMU and GPU SMMU for sdm845. v7 of this patchset also removes interrupt-names from the driver and the existing DT changes per feedback from Rob Herring. This is based on : git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next with: https://lore.kernel.org/patchwork/patch/1018365/ This change requires the following dependencies: include/dt-bindings/power/qcom-rpmpd.h: https://patchwork.kernel.org/patch/10711119/ qcom,smmu-v2 binding: https://patchwork.kernel.org/patch/10581911/ v7: Add patches to remove interrupt-names, add version specific compatible string for gmu v6: Update GPU bindings for a6xx and make the examples match the nodes and vice versa. Clean up types and rebase on https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging. v5: Use symbolic names for the RPMH power levels defined in OPP table, move the opp tables as children of their respective nodes and rename the iommu device. v4: Rebase v3: Split GMU PDC region into two GPU specific sections, fix indentation, really use qcom,gmu for the phandle name v2: changed qcom,arc-level to qcom,level following discussion with Viresh; change gmu phandle to qcom,gmu per Rob Jordan Crouse (6): drm/msm/gpu: Remove hardcoded interrupt name drm/msm: drop interrupt-names ARM: dts: qcom: Removed unused interrupt-names from GPU node arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings arm64: dts: sdm845: Add gpu and gmu device nodes .../devicetree/bindings/display/msm/gmu.txt | 59 +++++++++ .../devicetree/bindings/display/msm/gpu.txt | 43 +++++- arch/arm/boot/dts/qcom-apq8064.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 ++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 - drivers/gpu/drm/msm/msm_gpu.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 1 - 8 files changed, 221 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt