From patchwork Mon Mar 7 12:25:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmlhLXdlaSBDaGFuZyAo5by15L2z5YGJKQ==?= X-Patchwork-Id: 12771707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA978C433FE for ; Mon, 7 Mar 2022 12:25:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233647AbiCGM0R (ORCPT ); Mon, 7 Mar 2022 07:26:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232966AbiCGM0Q (ORCPT ); Mon, 7 Mar 2022 07:26:16 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9A607DAA7; Mon, 7 Mar 2022 04:25:21 -0800 (PST) X-UUID: b9b3713de332428c870e7a68727f2a51-20220307 X-UUID: b9b3713de332428c870e7a68727f2a51-20220307 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2142253048; Mon, 07 Mar 2022 20:25:15 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 7 Mar 2022 20:25:14 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Mar 2022 20:25:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 7 Mar 2022 20:25:13 +0800 From: Tim Chang To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Matthias Brugger , "Liam Girdwood" , Mark Brown , "Jia-Wei Chang" CC: , , , , , , , , , , Subject: [PATCH 0/3] devfreq: mediatek: introduce MTK cci devfreq Date: Mon, 7 Mar 2022 20:25:10 +0800 Message-ID: <20220307122513.11822-1-jia-wei.chang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Cache Coherent Interconnect (CCI) is the management of cache coherency by hardware. CCI DEVFREQ is DVFS driver for power saving by scaling clock frequency and supply voltage of CCI. CCI uses the same input clock source and power rail as LITTLE CPUs on Mediatek SoCs. Jia-Wei Chang (3): dt-bindings: devfreq: mediatek: add mtk cci devfreq dt-bindings devfreq: mediatek: add mt8183 cci devfreq driver devfreq: mediatek: add platform data to support mt8186 .../devicetree/bindings/devfreq/mtk-cci.yaml | 73 +++ drivers/devfreq/Kconfig | 11 +- drivers/devfreq/Makefile | 2 +- drivers/devfreq/mtk-cci-devfreq.c | 481 ++++++++++++++++++ 4 files changed, 565 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/devfreq/mtk-cci.yaml create mode 100644 drivers/devfreq/mtk-cci-devfreq.c