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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v3 00/14] Add support for AMD hardware feedback interface Date: Tue, 15 Oct 2024 16:36:31 -0500 Message-ID: <20241015213645.1476-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|SA3PR12MB7952:EE_ X-MS-Office365-Filtering-Correlation-Id: 136d0a05-0fd2-4bd9-7a24-08dced618d6e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 0V9p1bY950KR5+QfuFKHAW+mi0PWXvASVjiJxBuubfcUN7wyxLAIR2qaEeS+eCzkjAqjeaVMmKAjW+upnZobmQn2wkHfbFyPQw9bmrAb35jFqkiCkZdLsRuudC/JjNHKIy+tVYgZwmF2DDqK8RqGPN/trK6UDqnGyUrO23bRIpatcDM+g3FnRUHylK5PKZbNkX3QEOMHWzA5pM41p5IzIo+9w5vh0Wrl6dHge8UwCNEWeS0vg3YXorxxGP1/fh7Z6lBbkB+Tfcbj82nUISNjntZLhj1cXlfJIK77+CZdTg/0yMsLjK4xEe8EUB87ELxtR/JAT9jHJn1LJwCWDwdF5QfFElCQiWakcKSxa4DOrBnlE+x/Pqm1xjUasVKJkGzCwj+ELxBpf9NAr4TnD6Q/Fy4tpChSsssNS+y04b/AwE+3xDWy1BfXY1Wi8F3yL2Z6NavAfUNQ0XqfUlNZXdExZdWW8WY6YW7562gXcS2fDFNyVaWP4EyIaET31S01HYFE0rxj04KtxaBjjrGOGdH/JC9hUw8HCtXVpI8dGqZWNk8d7VjBHTdVwqYz1P75yAzay+rJza3lWWlkyrzRCk33sJ/4ctvJa4zNZ1Ecbcr5zGFbduX6XTlpoFPTlPNZiJsoDgkYZMfblx2nO0N+fUWVXT3cUoFHw4dl9RVp4fyqrFVlvccutG55G3R+0Wt3CKPungdlx3z4kdvQi74aN+oiNFvG8/2ah9YM9+xIa6xM0zk2GQpKD1o6LMBKcZ+d10Ybbk5lo9GV07ZmalLgpS2D/jtMiyJSMdEBFJKJXsx7kvX0gZl79RJ+/qBl9AzwdfBqd1/e057//U9hw6I4xaHeYK/sEzMnJ5bt9+9vWtSLv4n35JEN8EsEooTDSGKBPDPP3KgDh6To4/JpMm3SWl0KPEu3KAMU9tNRLAfsFPyatycjNhZiONF36i5Uv+YeWBg9Ufc9oQE2ZOILcbqlris1MI8nnS7z1B6Aui0ua35QbthUzjThAssQ1W6FuLnpeK3Ff4BfPor13kR4zL7DN4UVUUVUTPXC5600Q9vbSlQizjBCNhDkda7TbC0NswkImzIcA8RLUcBzScs7VPliMvjjcPUqdd/l19fTX2Mlvqrww4FuP6sL7f1L62LNqp0fbN5z8IllhWFDhKSzO8GBrNYcWEdJ1VCkB559Goy9x+JmSNIus/mm7TEN3+KtStjn8P44fnZyCvvDWTo4RDPz5hXrSkvB75JRNmMSEE7yJwkuf6p/EjTygeNOvjZC5ShwkKy05wtcN6a/8J/F3xvTBTDEKyZ0qNxfWOVUpgrAjjBsID8cw9/RzxP6lhqcjJ7hm5i6erNZdD0bvz+YltcntuhiUn2msTgnEO4K/nQ3IOHQZwr3PkwaSoqK62bvv57KRVVi X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2024 21:37:21.9581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 136d0a05-0fd2-4bd9-7a24-08dced618d6e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7952 The AMD Heterogeneous core design and Hardware Feedback Interface (HFI) provide behavioral classification and a dynamically updated ranking table for the scheduler to use when choosing cores for tasks. Threads are classified during runtime into enumerated classes. Currently, the driver supports 3 classes (0 through 2). These classes represent thread performance/power characteristics that may benefit from special scheduling behaviors. The real-time thread classification is consumed by the operating system and is used to inform the scheduler of where the thread should be placed for optimal performance or energy efficiency. The thread classification helps to select CPU from a ranking table that describes an efficiency and performance ranking for each classification from two dimensions. The ranking data provided by the ranking table are numbers ranging from 0 to 255, where a higher performance value indicates higher performance capability and a higher efficiency value indicates greater efficiency. All the CPU cores are ranked into different class IDs. Within each class ranking, the cores may have different ranking values. Therefore, picking from each classification ID will later allow the scheduler to select the best core while threads are classified into the specified workload class. This series was originally submitted by Perry Yuan [1] but he is now doing a different role and he asked me to take over. Link: https://lore.kernel.org/all/cover.1724748733.git.perry.yuan@amd.com/ On applicable hardware this series has between a 2% and 5% improvement across various benchmarks. There is however a cost associated with clearing history on the process context switch. On average it increases the delay by 119ns, and also has a wider range in delays (the standard deviation is 25% greater). Although this series most prominently has changes to platform-x86 it is based off of https://git.kernel.org/pub/scm/linux/kernel/git/superm1/linux.git/log/?h=linux-next due to changes queued up for 6.13-rc1 that are dependencies. --- v2->v3: * Take into mailing list feedback for various patches (see patches for details) * Add a patch to show the performance and efficiency rankings in debugfs Mario Limonciello (4): MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver cpufreq/amd-pstate: Disable preferred cores on designs with workload classification platform/x86/amd: hfi: Set ITMT priority from ranking data platform/x86: hfi: Add debugfs support Perry Yuan (10): Documentation: x86: Add AMD Hardware Feedback Interface documentation x86/cpufeatures: add X86_FEATURE_WORKLOAD_CLASS feature bit x86/msr-index: define AMD heterogeneous CPU related MSR platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver platform/x86: hfi: parse CPU core ranking data from shared memory platform/x86: hfi: init per-cpu scores for each class platform/x86: hfi: add online and offline callback support platform/x86: hfi: add power management callback x86/cpu: Enable SD_ASYM_PACKING for DIE Domain on AMD Processors x86/process: Clear hardware feedback history for AMD processors Documentation/arch/x86/amd-hfi.rst | 115 ++++++ Documentation/arch/x86/index.rst | 1 + MAINTAINERS | 9 + arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/hreset.h | 6 + arch/x86/include/asm/msr-index.h | 5 + arch/x86/kernel/cpu/common.c | 15 + arch/x86/kernel/cpu/scattered.c | 1 + arch/x86/kernel/process_32.c | 3 + arch/x86/kernel/process_64.c | 3 + arch/x86/kernel/smpboot.c | 5 +- drivers/cpufreq/amd-pstate.c | 6 + drivers/platform/x86/amd/Kconfig | 1 + drivers/platform/x86/amd/Makefile | 1 + drivers/platform/x86/amd/hfi/Kconfig | 21 + drivers/platform/x86/amd/hfi/Makefile | 7 + drivers/platform/x86/amd/hfi/hfi.c | 552 ++++++++++++++++++++++++++ 17 files changed, 750 insertions(+), 2 deletions(-) create mode 100644 Documentation/arch/x86/amd-hfi.rst create mode 100644 arch/x86/include/asm/hreset.h create mode 100644 drivers/platform/x86/amd/hfi/Kconfig create mode 100644 drivers/platform/x86/amd/hfi/Makefile create mode 100644 drivers/platform/x86/amd/hfi/hfi.c