From patchwork Tue Jul 30 18:00:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep KarkadaNagesha X-Patchwork-Id: 2835823 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D6F679F7D6 for ; Tue, 30 Jul 2013 18:00:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 72C4320356 for ; Tue, 30 Jul 2013 18:00:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5ADF620357 for ; Tue, 30 Jul 2013 18:00:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756546Ab3G3SAZ (ORCPT ); Tue, 30 Jul 2013 14:00:25 -0400 Received: from service87.mimecast.com ([91.220.42.44]:53253 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756085Ab3G3SAY (ORCPT ); Tue, 30 Jul 2013 14:00:24 -0400 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 30 Jul 2013 19:00:21 +0100 Received: from e103737-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 30 Jul 2013 19:00:19 +0100 From: Sudeep KarkadaNagesha To: cpufreq@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Cc: Sudeep.KarkadaNagesha@arm.com, Sudeep KarkadaNagesha , Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , "Rafael J. Wysocki" , Nishanth Menon Subject: [RFC PATCH 1/2] PM / OPP: add support to specify phandle of another node for OPP Date: Tue, 30 Jul 2013 19:00:16 +0100 Message-Id: <1375207217-4433-2-git-send-email-Sudeep.KarkadaNagesha@arm.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1375207217-4433-1-git-send-email-Sudeep.KarkadaNagesha@arm.com> References: <1375207217-4433-1-git-send-email-Sudeep.KarkadaNagesha@arm.com> X-OriginalArrivalTime: 30 Jul 2013 18:00:19.0357 (UTC) FILETIME=[A74474D0:01CE8D4E] X-MC-Unique: 113073019002103801 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sudeep KarkadaNagesha If more than one similar devices share the same OPPs, currently we need to replicate the OPP entries in all the nodes. Few drivers like cpufreq depend on physical cpu0 node to specify the OPPs and only that node is referred irrespective of the logical cpu accessing it. Alternatively to support cpuhotplug path, few drivers parse all the cpu nodes for OPPs. Instead we can specify the phandle of the node with which the current node shares the operating points. This patch adds support to specify the phandle in the operating points of any device node, where the node specified by the phandle holds the actual OPPs. Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: "Rafael J. Wysocki" Cc: Nishanth Menon Signed-off-by: Sudeep KarkadaNagesha --- Documentation/devicetree/bindings/power/opp.txt | 114 +++++++++++++++++++++--- drivers/base/power/opp.c | 12 ++- 2 files changed, 112 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 74499e5..f66fd65 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -4,22 +4,112 @@ SoCs have a standard set of tuples consisting of frequency and voltage pairs that the device will support per voltage domain. These are called Operating Performance Points or OPPs. -Properties: +Required Properties: - operating-points: An array of 2-tuples items, and each item consists of frequency and voltage like . freq: clock frequency in kHz vol: voltage in microvolt +Optional properties: +- operating-points-phandle: phandle to the device node with which this + device shares the operating points(recommended if multiple + devices are in the same clock domain and share OPPs, as it + avoids replication of OPPs) + Examples: -cpu@0 { - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 1100000 - 396000 950000 - 198000 850000 - >; -}; +1. A uniprocessor system + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + }; + +If more than one device of same type share the same OPPs, for example +all the CPUs on a SoC or in a single cluster on a SoC, then we need to +avoid replicating the OPPs in all the nodes. We can specify the phandle +of the node with which the current node shares the operating points instead. + +2. Consider a SMP system with 4 CPUs in the same clock domain. + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + operating-points-phandle = <&cpu0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + operating-points-phandle = <&cpu0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + operating-points-phandle = <&cpu0>; + }; + +3. Consider an AMP(asymmetric multi-processor) sytem with 2 clusters of CPUs. + Each cluster has 2 CPUs and all the CPUs within the cluster share the clock + domain. + + cpu0: cpu@0 { + compatible = "arm,cortex-a15"; + reg = <0>; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + clock-latency = <100000>; /* 100us */ + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a15"; + reg = <1>; + clock-latency = <100000>; /* 100us */ + operating-points-phandle = <&cpu0>; + }; + + cpu2: cpu@100 { + compatible = "arm,cortex-a7"; + reg = <100>; + operating-points = < + /* kHz uV */ + 792000 950000 + 396000 750000 + 198000 450000 + >; + clock-latency = <100000>; /* 100us */ + }; + + cpu3: cpu@101 { + compatible = "arm,cortex-a7"; + reg = <101>; + operating-points-phandle = <&cpu2>; + clock-latency = <100000>; /* 100us */ + }; diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c index c8ec186..9ac3c93 100644 --- a/drivers/base/power/opp.c +++ b/drivers/base/power/opp.c @@ -707,12 +707,20 @@ struct srcu_notifier_head *opp_get_notifier(struct device *dev) int of_init_opp_table(struct device *dev) { const struct property *prop; + struct device_node *opp_node; const __be32 *val; int nr; - prop = of_find_property(dev->of_node, "operating-points", NULL); - if (!prop) + opp_node = of_parse_phandle(dev->of_node, + "operating-points-phandle", 0); + if (!opp_node) /* if no OPP phandle, search for OPPs in current node */ + opp_node = dev->of_node; + prop = of_find_property(opp_node, "operating-points", NULL); + if (!prop) { + dev_warn(dev, "node %s missing operating-points property\n", + opp_node->full_name); return -ENODEV; + } if (!prop->value) return -ENODATA;