From patchwork Thu Nov 21 04:44:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 3216691 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 768109F3A0 for ; Thu, 21 Nov 2013 04:46:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 54CEB20780 for ; Thu, 21 Nov 2013 04:46:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 186A92077F for ; Thu, 21 Nov 2013 04:46:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751940Ab3KUEqT (ORCPT ); Wed, 20 Nov 2013 23:46:19 -0500 Received: from mail-pb0-f45.google.com ([209.85.160.45]:60164 "EHLO mail-pb0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751757Ab3KUEqR (ORCPT ); Wed, 20 Nov 2013 23:46:17 -0500 Received: by mail-pb0-f45.google.com with SMTP id rp16so4552024pbb.32 for ; Wed, 20 Nov 2013 20:46:17 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=8f/FovAqjDgiHfiggAZ+yqbChDWEyuX76xs9NyEQdvA=; b=f7UNKtVDPDf/YMcmqN8fjTsuoHCF2U2GgErmeS2gXy1+hrUTGepa9A7Nh26Q/PKYdi eBJ2/c0qGpqk/HTBy4xc2Fng4AJraCMA7NyDFqbByMvAAIo3q7I/yNdzEdo6DbIDQBis BLx5sOWVH3PtWREJvCXc8EF0tS3JSA6WGjwKKO0/IhU8tf0U3GplGcsX0oH78l81iey7 9kXmqlLDOwIcEVuC/gR2dP8aL82ZP71/qkFtoLl+yfvEoZqatavh0jg0bDMvDiVVJ0iG fjwknNWMu6sAj+BXiYOiijxQHDKQ1n5cq75w/7jLN0KgAU95zUeAwXryzid4IGpnn0Gd Q2KQ== X-Gm-Message-State: ALoCoQmxMItw1nFBn9piMv7wCi4muvGpFseOh4pEq3vdNuBLk5YXr3i7EezBJuRah3rwDFaOngGd X-Received: by 10.68.252.161 with SMTP id zt1mr4317165pbc.130.1385009177216; Wed, 20 Nov 2013 20:46:17 -0800 (PST) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id zq10sm47857352pab.6.2013.11.20.20.46.13 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 20 Nov 2013 20:46:16 -0800 (PST) From: Sachin Kamat To: linux-pm@vger.kernel.org Cc: cpufreq@vger.kernel.org, linux-samsung-soc@vger.kernel.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, kgene.kim@samsung.com, sachin.kamat@linaro.org, t.figa@samsung.com Subject: [PATCH 1/1] cpufreq: exynos5250: Set APLL rate using CCF API Date: Thu, 21 Nov 2013 10:14:06 +0530 Message-Id: <1385009046-22070-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use common clock framework (CCF) APIs to set the clock rates instead of direct register manipulation. This now updates the sysfs entry (cpuinfo_cur_freq) correctly which did not reflect the correct value until now. While at it clean up the PLL s-div parameter setting as it is handled by the PLL driver. Signed-off-by: Sachin Kamat Acked-by: Viresh Kumar Reviewed-by: Lukasz Majewski --- To fully test this, the following 2 patches would be necessary: * clk: exynos5250: register APLL rate table http://www.spinics.net/lists/arm-kernel/msg285103.html * clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apll http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/24906 --- drivers/cpufreq/exynos5250-cpufreq.c | 74 +++++----------------------------- 1 file changed, 10 insertions(+), 64 deletions(-) diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c index 8feda86fe42c..86fb1a105601 100644 --- a/drivers/cpufreq/exynos5250-cpufreq.c +++ b/drivers/cpufreq/exynos5250-cpufreq.c @@ -102,12 +102,12 @@ static void set_clkdiv(unsigned int div_index) cpu_relax(); } -static void set_apll(unsigned int new_index, - unsigned int old_index) +static void set_apll(unsigned int index) { - unsigned int tmp, pdiv; + unsigned int tmp; + unsigned int freq = apll_freq_5250[index].freq; - /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ + /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ clk_set_parent(moutcore, mout_mpll); do { @@ -116,24 +116,9 @@ static void set_apll(unsigned int new_index, tmp &= 0x7; } while (tmp != 0x2); - /* 2. Set APLL Lock time */ - pdiv = ((apll_freq_5250[new_index].mps >> 8) & 0x3f); - - __raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK); + clk_set_rate(mout_apll, freq * 1000); - /* 3. Change PLL PMS values */ - tmp = __raw_readl(EXYNOS5_APLL_CON0); - tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); - tmp |= apll_freq_5250[new_index].mps; - __raw_writel(tmp, EXYNOS5_APLL_CON0); - - /* 4. wait_lock_time */ - do { - cpu_relax(); - tmp = __raw_readl(EXYNOS5_APLL_CON0); - } while (!(tmp & (0x1 << 29))); - - /* 5. MUX_CORE_SEL = APLL */ + /* MUX_CORE_SEL = APLL */ clk_set_parent(moutcore, mout_apll); do { @@ -141,55 +126,17 @@ static void set_apll(unsigned int new_index, tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU); tmp &= (0x7 << 16); } while (tmp != (0x1 << 16)); - -} - -static bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index) -{ - unsigned int old_pm = apll_freq_5250[old_index].mps >> 8; - unsigned int new_pm = apll_freq_5250[new_index].mps >> 8; - - return (old_pm == new_pm) ? 0 : 1; } static void exynos5250_set_frequency(unsigned int old_index, unsigned int new_index) { - unsigned int tmp; - if (old_index > new_index) { - if (!exynos5250_pms_change(old_index, new_index)) { - /* 1. Change the system clock divider values */ - set_clkdiv(new_index); - /* 2. Change just s value in apll m,p,s value */ - tmp = __raw_readl(EXYNOS5_APLL_CON0); - tmp &= ~(0x7 << 0); - tmp |= apll_freq_5250[new_index].mps & 0x7; - __raw_writel(tmp, EXYNOS5_APLL_CON0); - - } else { - /* Clock Configuration Procedure */ - /* 1. Change the system clock divider values */ - set_clkdiv(new_index); - /* 2. Change the apll m,p,s value */ - set_apll(new_index, old_index); - } + set_clkdiv(new_index); + set_apll(new_index); } else if (old_index < new_index) { - if (!exynos5250_pms_change(old_index, new_index)) { - /* 1. Change just s value in apll m,p,s value */ - tmp = __raw_readl(EXYNOS5_APLL_CON0); - tmp &= ~(0x7 << 0); - tmp |= apll_freq_5250[new_index].mps & 0x7; - __raw_writel(tmp, EXYNOS5_APLL_CON0); - /* 2. Change the system clock divider values */ - set_clkdiv(new_index); - } else { - /* Clock Configuration Procedure */ - /* 1. Change the apll m,p,s value */ - set_apll(new_index, old_index); - /* 2. Change the system clock divider values */ - set_clkdiv(new_index); - } + set_apll(new_index); + set_clkdiv(new_index); } } @@ -222,7 +169,6 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) info->volt_table = exynos5250_volt_table; info->freq_table = exynos5250_freq_table; info->set_freq = exynos5250_set_frequency; - info->need_apll_change = exynos5250_pms_change; return 0;