From patchwork Wed Apr 16 14:15:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 4001861 X-Patchwork-Delegate: rui.zhang@intel.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A2E379F375 for ; Wed, 16 Apr 2014 14:16:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 081E42034A for ; Wed, 16 Apr 2014 14:16:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12D0A20340 for ; Wed, 16 Apr 2014 14:16:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161421AbaDPOQO (ORCPT ); Wed, 16 Apr 2014 10:16:14 -0400 Received: from top.free-electrons.com ([176.31.233.9]:48903 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1161272AbaDPOQN (ORCPT ); Wed, 16 Apr 2014 10:16:13 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id F1BF0808; Wed, 16 Apr 2014 16:16:12 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (unknown [190.2.108.73]) by mail.free-electrons.com (Postfix) with ESMTPSA id 9FDB560F; Wed, 16 Apr 2014 16:16:08 +0200 (CEST) From: Ezequiel Garcia To: , , Zhang Rui , Jason Cooper Cc: Sebastian Hesselbarth , Andrew Lunn , Arnd Bergmann , , Thomas Petazzoni , Gregory Clement , Jason Gunthorpe , Lior Amsalem , Tawfik Bayouk , Ezequiel Garcia Subject: [PATCH 4/6] thermal: armada: Support Armada 375 SoC Date: Wed, 16 Apr 2014 11:15:18 -0300 Message-Id: <1397657720-10893-5-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1397657720-10893-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1397657720-10893-1-git-send-email-ezequiel.garcia@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Now that a generic infrastructure is in place, it's possible to support the new Armada 375 SoC thermal sensor. This sensor is similar to the one available in the already supported SoCs, with its specific temperature formula and specific sensor initialization. In addition, we also add support for the Z1 SoC stepping, which needs an initialization-quirk to work properly. Signed-off-by: Ezequiel Garcia --- .../devicetree/bindings/thermal/armada-thermal.txt | 7 ++ drivers/thermal/armada_thermal.c | 83 ++++++++++++++++++++++ 2 files changed, 90 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt index fff93d5..745d241 100644 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt @@ -4,8 +4,15 @@ Required properties: - compatible: Should be set to one of the following: marvell,armada370-thermal + marvell,armada375-thermal + marvell,armada375-z1-thermal marvell,armadaxp-thermal + Note: As the name suggests, "marvell,armada375-z1-thermal" + applies for the SoC Z1 stepping only. The operating system + may auto-detect the SoC stepping and update the compatible + at runtime. + - reg: Device's register space. Two entries are expected, see the examples below. The first one is required for the sensor register; diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c index 3e4d8ef..a37942b 100644 --- a/drivers/thermal/armada_thermal.c +++ b/drivers/thermal/armada_thermal.c @@ -35,6 +35,15 @@ #define PMU_TDC0_OTF_CAL_MASK (0x1 << 30) #define PMU_TDC0_START_CAL_MASK (0x1 << 25) +#define A375_Z1_CAL_RESET_LSB 0x8011e214 +#define A375_Z1_CAL_RESET_MSB 0x30a88019 +#define A375_Z1_WORKAROUND_BIT BIT(9) + +#define TSEN40_UNIT_CONTROL_OFFSET 27 +#define TSEN40_UNIT_CONTROL_MASK 0x7 +#define TSEN40_READOUT_INVERT BIT(15) +#define TSEN40_HW_RESETn BIT(8) + struct armada_thermal_data; /* Marvell EBU Thermal Sensor Dev Structure */ @@ -106,6 +115,50 @@ static void armada370_init_sensor(struct armada_thermal_priv *priv) mdelay(10); } +static void armada375_init_sensor(struct armada_thermal_priv *priv) +{ + unsigned long reg; + + reg = readl(priv->control + 4); + reg &= ~(TSEN40_UNIT_CONTROL_MASK << TSEN40_UNIT_CONTROL_OFFSET); + reg &= ~TSEN40_READOUT_INVERT; + reg &= ~TSEN40_HW_RESETn; + + writel(reg, priv->control + 4); + mdelay(20); + + reg |= TSEN40_HW_RESETn; + writel(reg, priv->control + 4); + mdelay(50); +} + +static void armada375_z1_init_sensor(struct armada_thermal_priv *priv) +{ + unsigned long reg; + + /* + * On A375 Z1 SoC silicon revision the default (reset) values + * must be written. + */ + writel(A375_Z1_CAL_RESET_LSB, priv->control); + writel(A375_Z1_CAL_RESET_MSB, priv->control + 0x4); + + reg = readl(priv->control + 4); + reg &= ~(TSEN40_UNIT_CONTROL_MASK << TSEN40_UNIT_CONTROL_OFFSET); + reg &= ~TSEN40_READOUT_INVERT; + reg &= ~TSEN40_HW_RESETn; + + /* This is only needed on A375 Z1 SoC silicon revision */ + reg |= A375_Z1_WORKAROUND_BIT; + + writel(reg, priv->control + 4); + mdelay(20); + + reg |= TSEN40_HW_RESETn; + writel(reg, priv->control + 4); + mdelay(50); +} + static bool armada_is_valid(struct armada_thermal_priv *priv) { unsigned long reg = readl_relaxed(priv->sensor); @@ -163,6 +216,28 @@ static const struct armada_thermal_data armada370_data = { .coef_div = 13825, }; +static const struct armada_thermal_data armada375_data = { + .is_valid = armada_is_valid, + .init_sensor = armada375_init_sensor, + .is_valid_offset = 10, + .temp_offset = 0, + .temp_mask = 0x1ff, + .coef_b = 3171900000UL, + .coef_m = 10000000UL, + .coef_div = 13616, +}; + +static const struct armada_thermal_data armada375_z1_data = { + .is_valid = armada_is_valid, + .init_sensor = armada375_z1_init_sensor, + .is_valid_offset = 10, + .temp_offset = 0, + .temp_mask = 0x1ff, + .coef_b = 3171900000UL, + .coef_m = 10000000UL, + .coef_div = 13616, +}; + static const struct of_device_id armada_thermal_id_table[] = { { .compatible = "marvell,armadaxp-thermal", @@ -173,6 +248,14 @@ static const struct of_device_id armada_thermal_id_table[] = { .data = &armada370_data, }, { + .compatible = "marvell,armada375-thermal", + .data = &armada375_data, + }, + { + .compatible = "marvell,armada375-z1-thermal", + .data = &armada375_z1_data, + }, + { /* sentinel */ }, };