From patchwork Mon Jul 7 14:51:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 4495491 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 11A41BEEAA for ; Mon, 7 Jul 2014 14:52:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 26C0A20265 for ; Mon, 7 Jul 2014 14:51:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 496BF20357 for ; Mon, 7 Jul 2014 14:51:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753508AbaGGOvx (ORCPT ); Mon, 7 Jul 2014 10:51:53 -0400 Received: from top.free-electrons.com ([176.31.233.9]:57815 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753457AbaGGOvw (ORCPT ); Mon, 7 Jul 2014 10:51:52 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id 796432321; Mon, 7 Jul 2014 16:51:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id E1DDB7DB; Mon, 7 Jul 2014 16:51:51 +0200 (CEST) From: Thomas Petazzoni To: Mike Turquette , Viresh Kumar , "Rafael J. Wysocki" , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tawfik Bayouk , Nadav Haklai , Lior Amsalem , Ezequiel Garcia , Thomas Petazzoni Subject: [PATCHv2 5/8] ARM: mvebu: update Armada XP DT for dynamic frequency scaling Date: Mon, 7 Jul 2014 16:51:39 +0200 Message-Id: <1404744702-32010-6-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1404744702-32010-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1404744702-32010-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to support dynamic frequency scaling: * the cpuclk Device Tree node needs to be updated to describe a second set of registers describing the PMU DFS registers. * the clock-latency property of the CPUs must be filled, otherwise the ondemand and conservative cpufreq governors refuse to work. The latency is high because the cost of a frequency transition is quite high on those CPUs. Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 2 ++ arch/arm/boot/dts/armada-xp-mv78260.dtsi | 2 ++ arch/arm/boot/dts/armada-xp-mv78460.dtsi | 4 ++++ arch/arm/boot/dts/armada-xp.dtsi | 2 +- 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 1257ff1..2592e1c 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -34,6 +34,7 @@ compatible = "marvell,sheeva-v7"; reg = <0>; clocks = <&cpuclk 0>; + clock-latency = <1000000>; }; cpu@1 { @@ -41,6 +42,7 @@ compatible = "marvell,sheeva-v7"; reg = <1>; clocks = <&cpuclk 1>; + clock-latency = <1000000>; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 3396b25..480e237 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -36,6 +36,7 @@ compatible = "marvell,sheeva-v7"; reg = <0>; clocks = <&cpuclk 0>; + clock-latency = <1000000>; }; cpu@1 { @@ -43,6 +44,7 @@ compatible = "marvell,sheeva-v7"; reg = <1>; clocks = <&cpuclk 1>; + clock-latency = <1000000>; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 6da84bf..2c7b1fe 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -37,6 +37,7 @@ compatible = "marvell,sheeva-v7"; reg = <0>; clocks = <&cpuclk 0>; + clock-latency = <1000000>; }; cpu@1 { @@ -44,6 +45,7 @@ compatible = "marvell,sheeva-v7"; reg = <1>; clocks = <&cpuclk 1>; + clock-latency = <1000000>; }; cpu@2 { @@ -51,6 +53,7 @@ compatible = "marvell,sheeva-v7"; reg = <2>; clocks = <&cpuclk 2>; + clock-latency = <1000000>; }; cpu@3 { @@ -58,6 +61,7 @@ compatible = "marvell,sheeva-v7"; reg = <3>; clocks = <&cpuclk 3>; + clock-latency = <1000000>; }; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 5902e83..bff9f6c 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -99,7 +99,7 @@ cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,armada-xp-cpu-clock"; - reg = <0x18700 0xA0>; + reg = <0x18700 0xA0>, <0x1c054 0x10>; clocks = <&coreclk 1>; };