From patchwork Thu Jul 10 21:42:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tuomas Tynkkynen X-Patchwork-Id: 4526971 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EB51F9F1C4 for ; Thu, 10 Jul 2014 21:46:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 232B52012E for ; Thu, 10 Jul 2014 21:46:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C33E200F0 for ; Thu, 10 Jul 2014 21:46:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753040AbaGJVnn (ORCPT ); Thu, 10 Jul 2014 17:43:43 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:13936 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753023AbaGJVnl (ORCPT ); Thu, 10 Jul 2014 17:43:41 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 10 Jul 2014 14:43:10 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 10 Jul 2014 14:32:45 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 10 Jul 2014 14:32:45 -0700 Received: from ttynkkynen-lnx.Nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.342.0; Thu, 10 Jul 2014 14:43:40 -0700 From: Tuomas Tynkkynen To: , , , CC: Stephen Warren , Thierry Reding , Peter De Schrijver , Prashant Gaikwad , Mike Turquette , "Rafael J. Wysocki" , Viresh Kumar , , Tuomas Tynkkynen Subject: [PATCH 07/13] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Date: Fri, 11 Jul 2014 00:42:43 +0300 Message-ID: <1405028569-14253-8-git-send-email-ttynkkynen@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1405028569-14253-1-git-send-email-ttynkkynen@nvidia.com> References: <1405028569-14253-1-git-send-email-ttynkkynen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Save and restore this register since the LP1 restore assembly routines fiddle with it. Otherwise the CPU would keep running on PLLX after resume from suspend even when DFLL was the original clocksource. Signed-off-by: Tuomas Tynkkynen --- drivers/clk/tegra/clk-tegra124.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 77fbf38..758a4cf 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -89,6 +89,8 @@ #define PMC_PLLM_WB0_OVERRIDE 0x1dc #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 +#define CCLKG_BURST_POLICY 0x368 + #define UTMIP_PLL_CFG2 0x488 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) @@ -121,6 +123,8 @@ #ifdef CONFIG_PM_SLEEP static struct cpu_clk_suspend_context { u32 clk_csite_src; + u32 cclkg_burst; + u32 cclkg_divider; } tegra124_cpu_clk_sctx; #endif @@ -1318,12 +1322,22 @@ static void tegra124_cpu_clock_suspend(void) tegra124_cpu_clk_sctx.clk_csite_src = readl(clk_base + CLK_SOURCE_CSITE); writel(3 << 30, clk_base + CLK_SOURCE_CSITE); + + tegra124_cpu_clk_sctx.cclkg_burst = + readl(clk_base + CCLKG_BURST_POLICY); + tegra124_cpu_clk_sctx.cclkg_divider = + readl(clk_base + CCLKG_BURST_POLICY + 4); } static void tegra124_cpu_clock_resume(void) { writel(tegra124_cpu_clk_sctx.clk_csite_src, clk_base + CLK_SOURCE_CSITE); + + writel(tegra124_cpu_clk_sctx.cclkg_burst, + clk_base + CCLKG_BURST_POLICY); + writel(tegra124_cpu_clk_sctx.cclkg_divider, + clk_base + CCLKG_BURST_POLICY + 4); } #endif