From patchwork Mon Jul 21 15:39:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tuomas Tynkkynen X-Patchwork-Id: 4596581 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 08706C0514 for ; Mon, 21 Jul 2014 15:41:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C90212013D for ; Mon, 21 Jul 2014 15:41:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E7499200DB for ; Mon, 21 Jul 2014 15:41:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933140AbaGUPke (ORCPT ); Mon, 21 Jul 2014 11:40:34 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:11288 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933119AbaGUPkc (ORCPT ); Mon, 21 Jul 2014 11:40:32 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 21 Jul 2014 08:41:31 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 21 Jul 2014 08:32:46 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 21 Jul 2014 08:32:46 -0700 Received: from ttynkkynen-lnx.Nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.342.0; Mon, 21 Jul 2014 08:40:31 -0700 From: Tuomas Tynkkynen To: , , , CC: Stephen Warren , Thierry Reding , Peter De Schrijver , Prashant Gaikwad , Mike Turquette , "Rafael J. Wysocki" , Viresh Kumar , Paul Walmsley , , Tuomas Tynkkynen Subject: [PATCH v2 15/16] ARM: tegra: Add entries for cpufreq on Tegra124 Date: Mon, 21 Jul 2014 18:39:01 +0300 Message-ID: <1405957142-19416-16-git-send-email-ttynkkynen@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com> References: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Tegra124 cpufreq driver relies on certain clocks being present in the /cpus/cpu@0 node. Signed-off-by: Tuomas Tynkkynen --- v2 changes: - The clock-latency property was added, as cpufreq-cpu0 wants that arch/arm/boot/dts/tegra124.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 8ff4332..db51438 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -786,6 +786,15 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + + clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, + <&tegra_car TEGRA124_CLK_CCLK_LP>, + <&tegra_car TEGRA124_CLK_PLL_X>, + <&tegra_car TEGRA124_CLK_PLL_P>, + <&dfll>; + clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency = <300000>; }; cpu@1 {