From patchwork Wed Aug 20 20:41:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Soren Brinkmann X-Patchwork-Id: 4753721 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BA1549F344 for ; Wed, 20 Aug 2014 20:45:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C6F372013A for ; Wed, 20 Aug 2014 20:45:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E0521200E6 for ; Wed, 20 Aug 2014 20:45:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753300AbaHTUoc (ORCPT ); Wed, 20 Aug 2014 16:44:32 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:34970 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752991AbaHTUmm (ORCPT ); Wed, 20 Aug 2014 16:42:42 -0400 Received: by mail-pa0-f46.google.com with SMTP id lj1so12895063pab.19 for ; Wed, 20 Aug 2014 13:42:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=4bhrHro11CA2kUCiv2MtyREggxDlWlpAtUFzm8HL8p4=; b=qGq2R2XrihwgkFWOEAyvIIscfZYUJdmMSxXvZcIORDeVvbz/aXSZtAZITz6oMbBs1T WgiRTasGnBE9LHRiDLWnKe32PKpHlEoejT92CKwX4fSa1rp6GcHbXkQka27M9NwaAuqs NCTYGqSiJwDJhAlGx4VTisi4Kkfoze69GpLe1DvHlHp/XDKCK3qFKNJv3DJ8qcB2Ll0M cwBRn90Q9JQMo2/PnAGDdJ7GW6g5DZ+WT9/Qrzzy/b2NpBeU1lm+mmmcCjHKJ1HXEhZm wsJATeJFyQbNcmxqq4rG0ghKiXr7QZNTT/0hS7hUS/3NJ+OeVFxazrZMERubsu0UMH2g zBnw== X-Received: by 10.69.31.234 with SMTP id kp10mr55927960pbd.138.1408567359066; Wed, 20 Aug 2014 13:42:39 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id k9sm35439816pdo.28.2014.08.20.13.42.37 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 20 Aug 2014 13:42:38 -0700 (PDT) From: Soren Brinkmann To: Michal Simek , Russell King , "Rafael J. Wysocki" , Daniel Lezcano , Rob Herring , Mark Rutland Cc: =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Pawel Moll , Ian Campbell , Kumar Gala Subject: [PATCH 4/9] ARM: zynq: PM: Enable DDR self-refresh and clock stop Date: Wed, 20 Aug 2014 13:41:50 -0700 Message-Id: <1408567315-28479-5-git-send-email-soren.brinkmann@xilinx.com> X-Mailer: git-send-email 2.0.1.1.gfbfc394 In-Reply-To: <1408567315-28479-1-git-send-email-soren.brinkmann@xilinx.com> References: <1408567315-28479-1-git-send-email-soren.brinkmann@xilinx.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DDR controller can detect idle periods and leverage low power features like self-refresh and clock stop. When new requests occur, the DDRC resumes normal operation. Signed-off-by: Soren Brinkmann --- arch/arm/mach-zynq/Makefile | 2 +- arch/arm/mach-zynq/common.c | 1 + arch/arm/mach-zynq/common.h | 2 ++ arch/arm/mach-zynq/pm.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-zynq/pm.c diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index 1b25d92ebf22..820dff6e1eba 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := common.o slcr.o +obj-y := common.o slcr.o pm.o CFLAGS_REMOVE_hotplug.o =-march=armv6k CFLAGS_hotplug.o =-Wa,-march=armv7-a -mcpu=cortex-a9 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 3cb7c198615a..6bd13e5ce6b7 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -101,6 +101,7 @@ static int __init zynq_get_revision(void) static void __init zynq_init_late(void) { zynq_core_pm_init(); + zynq_pm_late_init(); } /** diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index 596ef0b5067c..87945fa2a179 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -40,6 +40,8 @@ extern void __iomem *zynq_scu_base; /* Hotplug */ extern void zynq_platform_cpu_die(unsigned int cpu); +int zynq_pm_late_init(void); + static inline void zynq_core_pm_init(void) { /* A9 clock gating */ diff --git a/arch/arm/mach-zynq/pm.c b/arch/arm/mach-zynq/pm.c new file mode 100644 index 000000000000..19955917aac8 --- /dev/null +++ b/arch/arm/mach-zynq/pm.c @@ -0,0 +1,84 @@ +/* + * Zynq power management + * + * Copyright (C) 2012 - 2014 Xilinx + * + * Sören Brinkmann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include "common.h" + +/* register offsets */ +#define DDRC_CTRL_REG1_OFFS 0x60 +#define DDRC_DRAM_PARAM_REG3_OFFS 0x20 + +/* bitfields */ +#define DDRC_CLOCKSTOP_MASK BIT(23) +#define DDRC_SELFREFRESH_MASK BIT(12) + +static void __iomem *ddrc_base; + +/** + * zynq_pm_ioremap() - Create IO mappings + * @comp: DT compatible string + * Returns a pointer to the mapped memory or NULL. + * + * Remap the memory region for a compatible DT node. + */ +static void __iomem *zynq_pm_ioremap(const char *comp) +{ + struct device_node *np; + void __iomem *base = NULL; + + np = of_find_compatible_node(NULL, NULL, comp); + if (np) { + base = of_iomap(np, 0); + of_node_put(np); + } else { + pr_warn("%s: no compatible node found for '%s'\n", __func__, + comp); + } + + return base; +} + +int __init zynq_pm_late_init(void) +{ + u32 reg; + + ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); + if (!ddrc_base) { + pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); + } else { + /* + * Enable DDRC self-refresh and clock stop features. The HW + * takes care of entering/exiting the correct modes depending + * on activity state. + */ + reg = readl(ddrc_base + DDRC_CTRL_REG1_OFFS); + reg |= DDRC_SELFREFRESH_MASK; + writel(reg, ddrc_base + DDRC_CTRL_REG1_OFFS); + + reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); + reg |= DDRC_CLOCKSTOP_MASK; + writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); + } + + return 0; +}