From patchwork Wed Oct 8 20:11:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Chaugule X-Patchwork-Id: 5055551 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 35F8AC11AB for ; Wed, 8 Oct 2014 20:11:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 363BB201BC for ; Wed, 8 Oct 2014 20:11:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 48B0320154 for ; Wed, 8 Oct 2014 20:11:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754636AbaJHULn (ORCPT ); Wed, 8 Oct 2014 16:11:43 -0400 Received: from mail-vc0-f178.google.com ([209.85.220.178]:60639 "EHLO mail-vc0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754969AbaJHULm (ORCPT ); Wed, 8 Oct 2014 16:11:42 -0400 Received: by mail-vc0-f178.google.com with SMTP id hq12so7290106vcb.23 for ; Wed, 08 Oct 2014 13:11:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YhAtgcRUA7Ln8DczJAbHAOyxsVu+G2vnIlm60MDfdp8=; b=buxR8VAUyI7XBrGkxwYnczBnVel8d3NipEOiRH3Xs2Hp2nYPMZhu5Zp7zJuNmg9ED9 mSJY1ZZfnfXSdcsnGQ6GweVObg9+71tTz6xj4Lt3ERz30OPdGERbcTqVwz8oAqfqFvf9 xq8g6Vh7ypOGHObLS7pbe82dPTpXmqC+VZ2OQQdLXeiLXOC0O9xKeF4tawJt54E1BApC Y3bg8uTY5xkE+ERzHwcShqIZU/jgEVOHGie3QtS5xdjlzRNnvqykTjxi9w9+PiS2gFsI J3uHjZ2CbpqIUPavpnsFkaqP6ShuXfoEVdLt4BvDL8IOpdcySTqamBHG78BnrctcT9AJ Kqhw== X-Gm-Message-State: ALoCoQm9yHxIrQr6uJnQqVNrDJmr21DvlzGDs3H4j7dKNiGVJzYvRQnwRI4ALQBxrvHblWv3JpsT X-Received: by 10.52.162.74 with SMTP id xy10mr11200460vdb.51.1412799102167; Wed, 08 Oct 2014 13:11:42 -0700 (PDT) Received: from localhost.localdomain (cpe-098-027-049-158.nc.res.rr.com. [98.27.49.158]) by mx.google.com with ESMTPSA id yf12sm946199vdc.18.2014.10.08.13.11.40 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Oct 2014 13:11:41 -0700 (PDT) From: Ashwin Chaugule To: viresh.kumar@linaro.org Cc: dirk.brandewie@gmail.com, rwells@codeaurora.org, rjw@rjwysocki.net, linaro-acpi@lists.linaro.org, linux-pm@vger.kernel.org, Catalin.Marinas@arm.com, linda.knippers@hp.com, Ashwin Chaugule Subject: [RFC PATCH v2 3/3] CPPC HACKS Date: Wed, 8 Oct 2014 16:11:04 -0400 Message-Id: <1412799064-2339-4-git-send-email-ashwin.chaugule@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1412799064-2339-1-git-send-email-ashwin.chaugule@linaro.org> References: <1412799064-2339-1-git-send-email-ashwin.chaugule@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Not for upstreaming. The IO space specified in the PCCT of the thinkpad doesn't seem to have anything behind it. So this patch creates a fake buffer shared between CPPC and PCC. Also, the write to DESIRED reg to indicate desired CPU performance level is an MSR on the Thinkpad (PERF_CTL). This is not specified by the CPC table on this laptop. So skip the cpc_write64() and directly write to the MSR. This avoids the deadlock situtaion where IRQs are disabled in the following path: mbox_send_message -> send_data -> pcc_send_data Signed-off-by: Ashwin Chaugule --- drivers/cpufreq/acpi_pid.c | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/acpi_pid.c b/drivers/cpufreq/acpi_pid.c index a6db149..f67dd8f 100644 --- a/drivers/cpufreq/acpi_pid.c +++ b/drivers/cpufreq/acpi_pid.c @@ -763,6 +763,8 @@ static int acpi_cppc_processor_probe(void) unsigned int num_ent, ret = 0, i, cpu, len; acpi_handle handle; acpi_status status; + //HACK: + u64 *tmp_buff; /* Parse the ACPI _CPC table for each cpu. */ for_each_possible_cpu(cpu) { @@ -850,19 +852,32 @@ static int acpi_cppc_processor_probe(void) pr_debug("From PCCT: CPPC subspace addr:%llx, len: %d\n", comm_base_addr, len); - pcc_comm_addr = ioremap(comm_base_addr, len); - if (!pcc_comm_addr) { + /* HACK: + * The IO space as specified by the PCCT on the Thinkpad + * doesn't seem to have anything behind it. So allocate + * a temp buff instead and use it between CPPC and PCC. + */ + tmp_buff = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (!tmp_buff) { + pr_err("Could not allocate temp PCC comm space\n"); ret = -ENOMEM; - pr_err("Failed to ioremap PCC comm region mem\n"); goto out_free; } +// pcc_comm_addr = ioremap(comm_base_addr, len); +// if (!pcc_comm_addr) { +// ret = -ENOMEM; +// pr_err("Failed to ioremap PCC comm region mem\n"); +// goto out_free; +// } /* * Overwrite it here for ease of use later in cpc_read/write calls * We dont really need the original address again anyway. */ - cppc_ss->base_address = (u64)pcc_comm_addr; - pr_debug("New PCC comm space addr: %llx\n", (u64)pcc_comm_addr); +// cppc_ss->base_address = (u64)pcc_comm_addr; + cppc_ss->base_address = (u64)tmp_buff; +// pr_debug("New PCC comm space addr: %llx\n", (u64)pcc_comm_addr); + pr_debug("New PCC comm space addr: %llx\n", (u64)tmp_buff); } else { pr_err("No pcc subspace detected in any CPC structure!\n"); @@ -985,7 +1000,20 @@ static int cppc_set_pstate(struct cpudata *cpudata, int state) } desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; - return cpc_write64(state, desired_reg); +// return cpc_write64(state, desired_reg); +/* HACK: Normally, the cpc_write64() would do the right thing, + * by writing to the DESIRED reg as specified by the CPC table. + * But, on this X240 laptop, the DESIRED reg is actually an MSR which + * is not defined in the CPC. So we could fake it inside the + * pcc_send_data() routine, but that wont work, since the + * mbox controller code disables IRQs before calling + * pcc_send_data(). This results in a deadlock, when that + * routine does a wrmsrl_on_cpu(). Directly call it here + * instead. Experimental anyway. + */ + val = state << 8; + wrmsrl_on_cpu(cpu, MSR_IA32_PERF_CTL, val); + return 0; } static struct cpu_defaults acpi_pid_cppc = {