From patchwork Thu Feb 26 13:21:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 5892551 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0A4CE9F37F for ; Thu, 26 Feb 2015 13:23:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1D9BD20398 for ; Thu, 26 Feb 2015 13:23:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 128B72020F for ; Thu, 26 Feb 2015 13:23:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753852AbbBZNWz (ORCPT ); Thu, 26 Feb 2015 08:22:55 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:36651 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932368AbbBZNWy (ORCPT ); Thu, 26 Feb 2015 08:22:54 -0500 Received: by pabkq14 with SMTP id kq14so13991362pab.3 for ; Thu, 26 Feb 2015 05:22:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qby8KiMUd+0mSHwu4Vzr5SASxazz1e3a6KXIVAZQUZk=; b=O7GCUvwqvrOVnQOyszSHKlQ4nLxH3bSoL0oAVgDmp/kPE+/aIl476ub3Oh8s31vQlH XBlSF0DQL1KR7XXwJf9IVUwXKDwXP1YPoxedIR3TFGqRqnuisrLFs5kJhxeRtQi+hPmc zOkEu9DleRgeMR8eFLAIQfg+Lzg59ExQ5vSkEIuNn4P/LB3SW71fPKZobMqBU5ubUDVO XuGWTMQI0pXPKBOCT/NHrCH1pZU84Q6Rrcxp3hQ0mxkvnWTC09mJXVZ87lCwxXV20tsr X//p+1snrNGjuCkQiScLg/kjKW3s33ZvyINg9NMQRFwBn/EP8iwR2t/3GY784sfq62ob HQxg== X-Gm-Message-State: ALoCoQmYn2/Zc8kgDtAvjgV+W84TNT/nwDOg2EVwQgzFGk4jM9F6D6X/668F27dFDt3oOAxEctLs X-Received: by 10.68.100.99 with SMTP id ex3mr5649812pbb.7.1424956973796; Thu, 26 Feb 2015 05:22:53 -0800 (PST) Received: from localhost.localdomain ([180.150.157.4]) by mx.google.com with ESMTPSA id g7sm1117723pdm.4.2015.02.26.05.22.50 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Feb 2015 05:22:53 -0800 (PST) From: Leo Yan To: "Rafael J . Wysocki" , Viresh Kumar , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Dan Zhao , zhenwei.wang@hisilicon.com, mohaoju@hisilicon.com Cc: Leo Yan Subject: [PATCH 2/2] dt-bindings: cpufreq: document for hisilicon acpu driver Date: Thu, 26 Feb 2015 21:21:39 +0800 Message-Id: <1424956899-8891-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1424956899-8891-1-git-send-email-leo.yan@linaro.org> References: <1424956899-8891-1-git-send-email-leo.yan@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds documentation for hisilicon acpu's cpufreq driver. OPP library is used for device tree parsing to get frequency list; Furthermore, this driver can bind all CPUs to change frequency together, or the two clusters can trigger the frequency change independently. This is controlled by the dtb flag "hisilicon,coupled-clusters". Signed-off-by: Leo Yan --- .../bindings/cpufreq/cpufreq-hisi-acpu.txt | 112 +++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-hisi-acpu.txt diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-hisi-acpu.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-hisi-acpu.txt new file mode 100644 index 0000000..547e7339 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-hisi-acpu.txt @@ -0,0 +1,112 @@ +Hisilicon acpu cpufreq driver +----------------------------- + +Hisilicon ACPU cpufreq driver for CPU frequency scaling. + +Required properties: +- operating-points: Table of frequencies and voltage CPU could be transitioned + into. Frequency should be in KHz units and voltage should be in + microvolts; This must be defined under node /cpus/cpu@x. Where x is + the first cpu inside a cluster. + +Optional properties: +- hisilicon,coupled-clusters: Specify whether all clusters share one clock + source. This must be defined under node cpufreq. + +Example 1: all clusters share one clock source +---------------------------------------------- + +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + operating-points = < + /* kHz uV */ + 1200000 0 + 960000 0 + 729000 0 + 432000 0 + 208000 0 + >; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + }; + + cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x100>; + }; + + cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x101>; + }; +}; + +cpufreq { + compatible = "hisilicon,hisi-acpu-cpufreq"; + hisilicon,coupled-clusters = <1>; +}; + + +Example 2: every cluster has dedicated clock source +--------------------------------------------------- + +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + operating-points = < + /* kHz uV */ + 1200000 0 + 960000 0 + 729000 0 + 432000 0 + 208000 0 + >; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + }; + + cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x100>; + operating-points = < + /* kHz uV */ + 1200000 0 + 960000 0 + 729000 0 + 432000 0 + 208000 0 + >; + }; + + cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x101>; + }; +}; + +cpufreq { + compatible = "hisilicon,hisi-acpu-cpufreq"; +};