From patchwork Sun Mar 1 12:44:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 5907671 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8BAC2BF6C3 for ; Sun, 1 Mar 2015 12:49:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B287220266 for ; Sun, 1 Mar 2015 12:49:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CA31520253 for ; Sun, 1 Mar 2015 12:49:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753369AbbCAMtC (ORCPT ); Sun, 1 Mar 2015 07:49:02 -0500 Received: from mail.kapsi.fi ([217.30.184.167]:54504 "EHLO mail.kapsi.fi" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752993AbbCAMtA (ORCPT ); Sun, 1 Mar 2015 07:49:00 -0500 Received: from [2001:708:30:12d0:beee:7bff:fe5b:f272] (helo=katsura.kyla.fi) by mail.kapsi.fi with esmtpsa (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1YS3I5-0007BU-9L; Sun, 01 Mar 2015 14:48:13 +0200 From: Mikko Perttunen To: swarren@wwwdotorg.org, thierry.reding@gmail.com, gnurou@gmail.com, pdeschrijver@nvidia.com, rjw@rjwysocki.net, viresh.kumar@linaro.org Cc: mturquette@linaro.org, pwalmsley@nvidia.com, vinceh@nvidia.com, pgaikwad@nvidia.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tuomas.tynkkynen@iki.fi, Mikko Perttunen Subject: [PATCH v8 10/18] clk: tegra: Initialize PLL_X before CCLK_G to ensure it has a parent Date: Sun, 1 Mar 2015 14:44:33 +0200 Message-Id: <1425213881-5262-11-git-send-email-mikko.perttunen@kapsi.fi> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1425213881-5262-1-git-send-email-mikko.perttunen@kapsi.fi> References: <1425213881-5262-1-git-send-email-mikko.perttunen@kapsi.fi> X-SA-Exim-Connect-IP: 2001:708:30:12d0:beee:7bff:fe5b:f272 X-SA-Exim-Mail-From: mikko.perttunen@kapsi.fi X-SA-Exim-Scanned: No (on mail.kapsi.fi); SAEximRunCond expanded to false Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch moves the initialization of PLL_X to be slightly before that of CCLK_G. This ensures that at boot, CCLK_G will immediately have a parent and the common clock framework can determine its clock rate correctly. Without this patch, calling clk_put on CCLK_G could cause the CCF to set its rate to zero, hanging the system. Signed-off-by: Mikko Perttunen --- v8: - Added drivers/clk/tegra/clk-tegra-super-gen4.c | 46 ++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index f1f4410..c5ea9ee 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -104,6 +104,32 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, struct clk *clk; struct clk **dt_clk; + /* + * Register PLL_X first so that CCLK_G has a parent at registration + * time. This ensures that the common clock framework knows CCLK_G's + * rate. + */ + +#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) + /* PLLX */ + dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks); + if (!dt_clk) + return; + + clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, + pmc_base, CLK_IGNORE_UNUSED, params, NULL); + *dt_clk = clk; + + /* PLLX_OUT0 */ + + dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks); + if (!dt_clk) + return; + clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", + CLK_SET_RATE_PARENT, 1, 2); + *dt_clk = clk; +#endif + /* CCLKG */ dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks); if (dt_clk) { @@ -127,25 +153,5 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, } tegra_sclk_init(clk_base, tegra_clks); - -#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) - /* PLLX */ - dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks); - if (!dt_clk) - return; - - clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, - pmc_base, CLK_IGNORE_UNUSED, params, NULL); - *dt_clk = clk; - - /* PLLX_OUT0 */ - - dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks); - if (!dt_clk) - return; - clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", - CLK_SET_RATE_PARENT, 1, 2); - *dt_clk = clk; -#endif }