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Fri, 11 Sep 2015 03:20:31 +0000 Received: from b51503-01.ap.freescale.net (b51503-01.ap.freescale.net [10.193.102.227]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t8B3KSR2000356; Thu, 10 Sep 2015 20:20:28 -0700 From: Bai Ping To: CC: , , Subject: [PATCH] cpufreq: imx: update the clock swith flow to support imx6ul Date: Fri, 11 Sep 2015 19:23:55 +0800 Message-ID: <1441970635-14297-1-git-send-email-b51503@freescale.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD007; 1:Edaf1MWciiD6CFWxUfjUHyg494zgji/RmEXP5Nt5vToAZfXfcOH2XbQXwDNbopCG4QTilBvb6hwIeK0pX2vMfdn8jBoQH4iop9EQ34bDXIo0wMNZyXq/BaMeNmdJWYRWzUKNyffczcKuBbkOR/1qRlR9XC+X8M9G21wPBoHQJLvhW73/t9+gmC9kzz2Bn4uaO5xnebs6M6Zbrk4XG/IGF0/mgNiEaQuC0m0W6dU6Z+rrgORxertxrkqhDPgjT/69IPpja7NweVUp5KY3nyQTmJxsXg62HqgMlVyLIWUDXYWSjaJdLxTs/BTtWAjCDDmsMZJ9Df3r45Zuwo+7K2BTwoQjLedRghYtSz1ohAFrWlZ3BcH9ogb5voC2dqfm1fL2 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; 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BY2PR03MB491; 5:4nCiYnhjEyrcbwKEDKpD4hXWQw7EQ7BdaqgmkJoMDjQodF78iYBC96F1pE5cZM9r9kLPlzDIreGJs+es8Hq0sQqqUizW9vaLIj58cZ28sCa+47AU0El1Y+1RTMYLzZS0C6YlZxISB4vjCI33Aw2MDw==; 24:a/+gtD1jld50LZgAW4tqMq9ZXDuC3ltnI+amk/dnwzRhtjpdUr/7rzdueYzmP1zJzHUyWz+b7Sx3SW2rxWUdeVmlD5D75HUI7ruAdvRPmaU=; 20:MPKh4BWnVpTW5gKgrLxczgHUgmHtslDfI1UFKzxvuwZGMglb+yhWxLsgk1bfIbN4HMSrKiP0/1pMFp6O4OXSQQ== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2015 03:20:31.3925 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR03MB491 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_HI,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For I.MX6UL, the clock change flow is slightly different from other I.MX6 SOCs. It has a 'secondary_sel' clk that will be used when the CPU freq is higher than 396MHz. So the clock change flow in 'set_target' callback need to update to support i.MX6UL in the common I.MX6 SOC cpufreq driver. Signed-off-by: Bai Ping --- drivers/cpufreq/imx6q-cpufreq.c | 48 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index 380a90d..2431b6d 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -30,6 +30,10 @@ static struct clk *pll1_sw_clk; static struct clk *step_clk; static struct clk *pll2_pfd2_396m_clk; +/* clk used by i.MX6UL */ +static struct clk *pll2_bus_clk; +static struct clk *secondary_sel_clk; + static struct device *cpu_dev; static bool free_opp; static struct cpufreq_frequency_table *freq_table; @@ -91,16 +95,36 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) * The setpoints are selected per PLL/PDF frequencies, so we need to * reprogram PLL for frequency scaling. The procedure of reprogramming * PLL1 is as below. - * + * For i.MX6UL, it has a secondary clk mux, the cpu frequency change + * flow is slightly different from other i.MX6 OSC. + * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it * - Disable pll2_pfd2_396m_clk */ - clk_set_parent(step_clk, pll2_pfd2_396m_clk); - clk_set_parent(pll1_sw_clk, step_clk); - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { - clk_set_rate(pll1_sys_clk, new_freq * 1000); + if (of_machine_is_compatible("fsl,imx6ul")) { + /* + * When changing pll1_sw_clk's parent to pll1_sys_clk, + * CPU may run at higher than 528MHz, this will lead to + * the system unstable if the voltage is lower than the + * voltage of 528MHz, so lower the CPU frequency to one + * half before changing CPU frequency. + */ + clk_set_rate(arm_clk, (old_freq >> 1) * 1000); clk_set_parent(pll1_sw_clk, pll1_sys_clk); + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) + clk_set_parent(secondary_sel_clk, pll2_bus_clk); + else + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); + clk_set_parent(step_clk, secondary_sel_clk); + clk_set_parent(pll1_sw_clk, step_clk); + } else { + clk_set_parent(step_clk, pll2_pfd2_396m_clk); + clk_set_parent(pll1_sw_clk, step_clk); + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { + clk_set_rate(pll1_sys_clk, new_freq * 1000); + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + } } /* Ensure the arm clock divider is what we expect */ @@ -186,6 +210,16 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) goto put_clk; } + if (of_machine_is_compatible("fsl,imx6ul")) { + pll2_bus_clk = clk_get(cpu_dev, "pll2_bus"); + secondary_sel_clk = clk_get(cpu_dev, "secondary_sel"); + if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) { + dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n"); + ret = -ENOENT; + goto put_clk; + } + } + arm_reg = regulator_get(cpu_dev, "arm"); pu_reg = regulator_get_optional(cpu_dev, "pu"); soc_reg = regulator_get(cpu_dev, "soc"); @@ -331,6 +365,10 @@ put_clk: clk_put(step_clk); if (!IS_ERR(pll2_pfd2_396m_clk)) clk_put(pll2_pfd2_396m_clk); + if (!IS_ERR(pll2_bus_clk)) + clk_put(pll2_bus_clk); + if (!IS_ERR(secondary_sel_clk)) + clk_put(secondary_sel_clk); of_node_put(np); return ret; }