From patchwork Thu Oct 22 12:02:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 7464721 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 897FE9F302 for ; Thu, 22 Oct 2015 12:04:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AD5B72094C for ; Thu, 22 Oct 2015 12:04:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 59D5A20943 for ; Thu, 22 Oct 2015 12:03:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756615AbbJVMDm (ORCPT ); Thu, 22 Oct 2015 08:03:42 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59405 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751774AbbJVMDM (ORCPT ); Thu, 22 Oct 2015 08:03:12 -0400 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1939527931; Thu, 22 Oct 2015 20:03:07 +0800 Received: from mtkslt303.mediatek.inc (10.21.14.116) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Thu, 22 Oct 2015 20:02:47 +0800 From: Dawei Chien To: Viresh Kumar CC: "Rafael J. Wysocki" , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Matthias Brugger , Daniel Kurtz , Sascha Hauer , Daniel Lezcano , Dawei Chien , , , , , , , Sascha Hauer Subject: [PATCH v3 1/2] thermal: mediatek: Add cpu power cooling model. Date: Thu, 22 Oct 2015 20:02:38 +0800 Message-ID: <1445515359-8587-2-git-send-email-dawei.chien@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1445515359-8587-1-git-send-email-dawei.chien@mediatek.com> References: <1445515359-8587-1-git-send-email-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This power model is base on Intelligent Power Allocation (IPA) technical, requires that the operating-points of the CPUs are registered using the kernel's opp library and the `cpufreq_frequency_table` is assigned to the `struct device` of the cpu MT8173. Signed-off-by: Dawei.Chien --- This patch is base on https://patchwork.kernel.org/patch/7034601/ --- drivers/cpufreq/mt8173-cpufreq.c | 152 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 144 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/mt8173-cpufreq.c b/drivers/cpufreq/mt8173-cpufreq.c index 49caed2..23c19c5 100644 --- a/drivers/cpufreq/mt8173-cpufreq.c +++ b/drivers/cpufreq/mt8173-cpufreq.c @@ -29,6 +29,16 @@ #define MAX_VOLT_LIMIT (1150000) #define VOLT_TOL (10000) +struct mtk_cpu_static_power { + unsigned long voltage; + unsigned int power; +}; + +static struct mtk_cpu_static_power *mtk_ca53_static_power_table; +static struct mtk_cpu_static_power *mtk_ca57_static_power_table; +static int mtk_ca53_static_table_length; +static int mtk_ca57_static_table_length; + /* * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in @@ -51,6 +61,110 @@ struct mtk_cpu_dvfs_info { bool need_voltage_tracking; }; +unsigned int mtk_cpufreq_lookup_power(const struct mtk_cpu_static_power *table, + unsigned int count, unsigned long voltage) +{ + int i; + + for (i = 0; i < count; i++) { + if (voltage <= table[i].voltage) + return table[i].power; + } + + return table[count - 1].power; +} + +int mtk_cpufreq_get_static(cpumask_t *cpumask, int interval, + unsigned long voltage, u32 *power) +{ + int nr_cpus = cpumask_weight(cpumask); + + *power = 0; + + if (nr_cpus) { + if (cpumask_test_cpu(0, cpumask)) + *power += mtk_cpufreq_lookup_power( + mtk_ca53_static_power_table, + mtk_ca53_static_table_length, + voltage); + + if (cpumask_test_cpu(2, cpumask)) + *power += mtk_cpufreq_lookup_power( + mtk_ca57_static_power_table, + mtk_ca57_static_table_length, + voltage); + } + + return 0; +} + +unsigned int mtk_get_power_table_info(struct cpufreq_policy *policy, + struct device_node *np, const char *node_name) +{ + int mtk_static_table_length; + const struct property *prop; + struct mtk_cpu_dvfs_info *info = policy->driver_data; + struct device *cpu_dev = info->cpu_dev; + const __be32 *val; + int nr, i; + + prop = of_find_property(np, node_name, NULL); + + if (!prop) { + pr_err("failed to get static-power-points\n"); + return -ENODEV; + } + + if (!prop->value) { + pr_err("failed to get static power array data\n"); + return -EINVAL; + } + + nr = prop->length / sizeof(u32); + + if (nr % 2) { + pr_err("Invalid OPP list\n"); + return -EINVAL; + } + + mtk_static_table_length = nr / 2; + + if (cpumask_test_cpu(0, policy->related_cpus)) { + mtk_ca53_static_table_length = mtk_static_table_length; + mtk_ca53_static_power_table = devm_kcalloc(cpu_dev, + mtk_static_table_length, + sizeof(*mtk_ca53_static_power_table), + GFP_KERNEL); + + val = prop->value; + for (i = 0; i < mtk_static_table_length; ++i) { + unsigned long voltage = be32_to_cpup(val++); + unsigned int power = be32_to_cpup(val++); + + mtk_ca53_static_power_table[i].voltage = voltage; + mtk_ca53_static_power_table[i].power = power; + pr_info("volt:%ld uv, power:%d mW\n", voltage, power); + } + } else { + mtk_ca57_static_table_length = mtk_static_table_length; + mtk_ca57_static_power_table = devm_kcalloc(cpu_dev, + mtk_static_table_length, + sizeof(*mtk_ca57_static_power_table), + GFP_KERNEL); + val = prop->value; + for (i = 0; i < mtk_static_table_length; ++i) { + unsigned long voltage = be32_to_cpup(val++); + unsigned int power = be32_to_cpup(val++); + + mtk_ca57_static_power_table[i].voltage = voltage; + mtk_ca57_static_power_table[i].power = power; + pr_info("volt:%ld uv, power:%d mW\n", voltage, power); + } + } + + return 0; +} + static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, int new_vproc) { @@ -267,20 +381,40 @@ static void mtk_cpufreq_ready(struct cpufreq_policy *policy) { struct mtk_cpu_dvfs_info *info = policy->driver_data; struct device_node *np = of_node_get(info->cpu_dev->of_node); + u32 capacitance; + int ret; if (WARN_ON(!np)) return; if (of_find_property(np, "#cooling-cells", NULL)) { - info->cdev = of_cpufreq_cooling_register(np, - policy->related_cpus); - if (IS_ERR(info->cdev)) { - dev_err(info->cpu_dev, - "running cpufreq without cooling device: %ld\n", - PTR_ERR(info->cdev)); + if (!info->cdev) { + + of_property_read_u32(np, + "dynamic-power-coefficient", + &capacitance); + + ret = mtk_get_power_table_info(policy, np, + "static-power-points"); + if (ret) { + dev_err(info->cpu_dev, + "cpufreq without static-points: %d\n", + ret); + } + + info->cdev = of_cpufreq_power_cooling_register(np, + policy->related_cpus, + capacitance, + mtk_cpufreq_get_static); + + if (IS_ERR(info->cdev)) { + dev_err(info->cpu_dev, + "cpufreq without cdev: %ld\n", + PTR_ERR(info->cdev)); + info->cdev = NULL; + } - info->cdev = NULL; } } @@ -460,7 +594,9 @@ static int mtk_cpufreq_exit(struct cpufreq_policy *policy) { struct mtk_cpu_dvfs_info *info = policy->driver_data; - cpufreq_cooling_unregister(info->cdev); + if (info->cdev) + cpufreq_cooling_unregister(info->cdev); + dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table); mtk_cpu_dvfs_info_release(info); kfree(info);