From patchwork Fri Oct 23 11:25:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 7472091 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CF2BEBEEA4 for ; Fri, 23 Oct 2015 11:26:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BB08920621 for ; Fri, 23 Oct 2015 11:26:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 38008206F3 for ; Fri, 23 Oct 2015 11:26:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753116AbbJWL0E (ORCPT ); Fri, 23 Oct 2015 07:26:04 -0400 Received: from mail-pa0-f67.google.com ([209.85.220.67]:34669 "EHLO mail-pa0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753059AbbJWLZ6 (ORCPT ); Fri, 23 Oct 2015 07:25:58 -0400 Received: by padda3 with SMTP id da3so12407404pad.1; Fri, 23 Oct 2015 04:25:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IQ4OM9zm/zAos5nBs96R2S0zAEcnATgL39R3EJgc1ZY=; b=MNAoIGm3FQaVIqHHhWofuOII3/STa9FOcTe/df+tUQMi7b/5ZOX/D7pyzOfi+PbjgY ofvWht5Cc1/VMHQlAn4psBxFPBdt471thUKvG6Fp0IampURA6IvfoTI2eW9QUvseU7NP BGIWZU3jmtzZclJIN6/OUXo/OKrRk/BartMQ0IiYS5A4KpilfA9/jHv6qF724ZuDbrmG Ole50uVBW1KjMCvPcTBfGthaKHUuvT99J7ZE5ZDkN00jx5lac/vpu1XDMj/nF0EwBbgu i2BMNMMA3LAv3nOsrVUNnhSQTAJJWCQg/yhPhKOm2zgYXCDhEBDEQ0KB0bXtShYQIVyp tdlA== X-Received: by 10.68.143.100 with SMTP id sd4mr4584858pbb.139.1445599557757; Fri, 23 Oct 2015 04:25:57 -0700 (PDT) Received: from localhost.localdomain ([103.47.144.9]) by smtp.gmail.com with ESMTPSA id oi3sm1394274pbb.53.2015.10.23.04.25.47 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Oct 2015 04:25:56 -0700 (PDT) From: Caesar Wang To: Heiko Stuebner Cc: Dmitry Torokhov , dianders@chromium.org, Eduardo Valentin , Caesar Wang , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Kumar Gala , linux-kernel@vger.kernel.org, Ian Campbell , linux-rockchip@lists.infradead.org, Rob Herring , linux-arm-kernel@lists.infradead.org, Pawel Moll , Zhang Rui , Mark Rutland Subject: [PATCH v4 1/3] dt-bindings: rockchip-thermal: Add the pinctrl states in this document Date: Fri, 23 Oct 2015 19:25:26 +0800 Message-Id: <1445599528-18825-2-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445599528-18825-1-git-send-email-wxt@rock-chips.com> References: <1445599528-18825-1-git-send-email-wxt@rock-chips.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The "init" pinctrl is defined we'll set pinctrl to this state before probe and then "default" after probe. Add the "init" and "sleep" pinctrl as the OTP gpio state, since we need switch the pin to gpio state before the TSADC controller is reset. AFAIK, the TSADC controller is reset, the tshut polarity will be a *low* signal in a short period of time for some devices. Says: The TSADC get the temperature on rockchip thermal. If T(current temperature) < (setting temperature), the OTP output the *high* signal. If T(current temperature) > (setting temperature), the OTP output the *low* Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. Signed-off-by: Caesar Wang Reviewed-by: Douglas Anderson Acked-by: Rob Herring --- Changes in v4: None Changes in v3: - Add the pictrl states decription in document. Changes in v2: - Add the 'init' pinctrl more decription in commit. - Fix the subject to make more obvious in PATCH[1/2] - Resend this patch v2 since fix the subject to be specific. Changes in v1: - As the Doug comments, add the 'init' property to sync document. .../devicetree/bindings/thermal/rockchip-thermal.txt | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt index ef802de..b38200d 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt @@ -12,6 +12,11 @@ Required properties: - resets : Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names : Must include the name "tsadc-apb". +- pinctrl-names : The pin control state names; +- pinctrl-0 : The "init" pinctrl state, it will be set before device probe. +- pinctrl-1 : The "default" pinctrl state, it will be set after reset the + TSADC controller. +- pinctrl-2 : The "sleep" pinctrl state, it will be in for suspend. - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. - rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. - rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. @@ -27,8 +32,10 @@ tsadc: tsadc@ff280000 { clock-names = "tsadc", "apb_pclk"; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; - pinctrl-names = "default"; - pinctrl-0 = <&otp_out>; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; #thermal-sensor-cells = <1>; rockchip,hw-tshut-temp = <95000>; rockchip,hw-tshut-mode = <0>;