From patchwork Fri Dec 4 14:57:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 7768811 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DD4EB9F30B for ; Fri, 4 Dec 2015 15:02:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0B26F20451 for ; Fri, 4 Dec 2015 15:02:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 22878205F3 for ; Fri, 4 Dec 2015 15:01:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752054AbbLDPBx (ORCPT ); Fri, 4 Dec 2015 10:01:53 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5636 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754390AbbLDPBR (ORCPT ); Fri, 4 Dec 2015 10:01:17 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 04 Dec 2015 07:01:22 -0800 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 04 Dec 2015 06:47:55 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 04 Dec 2015 06:47:55 -0800 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.406.0; Fri, 4 Dec 2015 07:01:15 -0800 From: Jon Hunter To: Philipp Zabel , Stephen Warren , Thierry Reding , Alexandre Courbot , Rafael Wysocki , Kevin Hilman , Ulf Hansson , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala CC: Vince Hsu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Jon Hunter Subject: [PATCH V4 15/16] ARM64: tegra: Add audio PM domain device node for Tegra210 Date: Fri, 4 Dec 2015 14:57:16 +0000 Message-ID: <1449241037-22193-16-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1449241037-22193-1-git-send-email-jonathanh@nvidia.com> References: <1449241037-22193-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the audio power-domain for tegra210. Note that this also removes the existing "#power-domain-cells" which was incorrectly included by commit e53095857166 ("arm64: tegra: Add Tegra210 support"). Signed-off-by: Jon Hunter --- So far I have only added the audio power-domain for tegra210 as this is what I have been testing with to date. However, once this series is accepted then we can begin to add more. --- arch/arm/boot/dts/tegra124.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 68669f791c8b..d868f4452c4e 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index bc23f4dea002..c5e9c320092b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include #include / { @@ -581,7 +582,15 @@ clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; - #power-domain-cells = <1>; + pm-domains { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + nvidia,powergate = ; + #power-domain-cells = <0>; + }; + }; }; fuse@0,7000f800 {