From patchwork Thu Jan 28 16:33:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 8152281 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2FC9CBEEE5 for ; Thu, 28 Jan 2016 16:34:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4975A20340 for ; Thu, 28 Jan 2016 16:34:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6349720328 for ; Thu, 28 Jan 2016 16:34:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1945954AbcA1Qeg (ORCPT ); Thu, 28 Jan 2016 11:34:36 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19852 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1945947AbcA1Qef (ORCPT ); Thu, 28 Jan 2016 11:34:35 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 28 Jan 2016 08:34:40 -0800 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 28 Jan 2016 08:35:10 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 28 Jan 2016 08:35:10 -0800 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.406.0; Thu, 28 Jan 2016 08:34:34 -0800 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala CC: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jon Hunter Subject: [PATCH V5 07/14] soc: tegra: pmc: Ensure partitions can be toggled on/off by PMC Date: Thu, 28 Jan 2016 16:33:45 +0000 Message-ID: <1453998832-27383-8-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1453998832-27383-1-git-send-email-jonathanh@nvidia.com> References: <1453998832-27383-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For Tegra124 and Tegra210, the GPU partition cannot be toggled on and off via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. For these devices, the partition is simply powered up and down via an external regulator. Describe in the PMC SoC data in which devices the GPU partition can be controlled via the APBDEV_PMC_PWRGATE_TOGGLE_0 register and ensure that no one can incorrectly try to toggle the GPU partition via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. Signed-off-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 032dd5c17130..ecb4f66819fd 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -110,6 +110,7 @@ struct tegra_pmc_soc { bool has_tsense_reset; bool has_gpu_clamps; + bool has_gpu_toggle; }; /** @@ -197,6 +198,9 @@ static int tegra_powergate_set(unsigned int id, bool new_state) bool status; int err; + if (id == TEGRA_POWERGATE_3D && !pmc->soc->has_gpu_toggle) + return -EINVAL; + mutex_lock(&pmc->powergates_lock); if (tegra_powergate_state(id) == new_state) { @@ -250,6 +254,9 @@ int tegra_powergate_is_powered(unsigned int id) if (!tegra_powergate_is_valid(id)) return -EINVAL; + if (id == TEGRA_POWERGATE_3D && !pmc->soc->has_gpu_toggle) + return -EINVAL; + mutex_lock(&pmc->powergates_lock); status = tegra_powergate_state(id); mutex_unlock(&pmc->powergates_lock); @@ -968,6 +975,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .cpu_powergates = tegra30_cpu_powergates, .has_tsense_reset = true, .has_gpu_clamps = false, + .has_gpu_toggle = true, }; static const char * const tegra114_powergates[] = { @@ -1005,6 +1013,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .cpu_powergates = tegra114_cpu_powergates, .has_tsense_reset = true, .has_gpu_clamps = false, + .has_gpu_toggle = true, }; static const char * const tegra124_powergates[] = { @@ -1048,6 +1057,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = { .cpu_powergates = tegra124_cpu_powergates, .has_tsense_reset = true, .has_gpu_clamps = true, + .has_gpu_toggle = false, }; static const char * const tegra210_powergates[] = { @@ -1091,6 +1101,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .cpu_powergates = tegra210_cpu_powergates, .has_tsense_reset = true, .has_gpu_clamps = true, + .has_gpu_toggle = false, }; static const struct of_device_id tegra_pmc_match[] = {