From patchwork Wed Mar 16 08:58:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 8596861 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 090EBC0553 for ; Wed, 16 Mar 2016 09:00:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2FFC920374 for ; Wed, 16 Mar 2016 09:00:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6C9CA2034B for ; Wed, 16 Mar 2016 09:00:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966271AbcCPI6T (ORCPT ); Wed, 16 Mar 2016 04:58:19 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5760 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965947AbcCPI6S (ORCPT ); Wed, 16 Mar 2016 04:58:18 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 16 Mar 2016 01:58:13 -0700 Received: from hqemhub03.nvidia.com ([172.20.150.15]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 16 Mar 2016 01:56:49 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 16 Mar 2016 01:56:49 -0700 Received: from HKMAIL101.nvidia.com (10.18.16.10) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.406.0; Wed, 16 Mar 2016 01:58:17 -0700 Received: from niwei-dev.nvidia.com (10.19.224.146) by HKMAIL101.nvidia.com (10.18.16.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 16 Mar 2016 08:58:12 +0000 From: Wei Ni To: , , CC: , , , , , , Wei Ni Subject: [PATCH V8 10/14] thermal: tegra: handle clocks in one function Date: Wed, 16 Mar 2016 16:58:26 +0800 Message-ID: <1458118706-29993-1-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.19.224.146] X-ClientProxiedBy: HKMAIL102.nvidia.com (10.18.16.11) To HKMAIL101.nvidia.com (10.18.16.10) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Handle clock enable/disable codes in one funcion soctherm_clk_enable(), so that the codes are more clear. Signed-off-by: Wei Ni --- drivers/thermal/tegra/soctherm.c | 51 ++++++++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c index 67e4a094b430..f60106884ac4 100644 --- a/drivers/thermal/tegra/soctherm.c +++ b/drivers/thermal/tegra/soctherm.c @@ -428,6 +428,39 @@ static void soctherm_debug_init(struct platform_device *pdev) static inline void soctherm_debug_init(struct platform_device *pdev) {} #endif +static int soctherm_clk_enable(struct platform_device *pdev, bool enable) +{ + struct tegra_soctherm *tegra = platform_get_drvdata(pdev); + int err; + + if (tegra->clock_soctherm == NULL || tegra->clock_tsensor == NULL) + return -EINVAL; + + reset_control_assert(tegra->reset); + + if (enable) { + err = clk_prepare_enable(tegra->clock_soctherm); + if (err) { + reset_control_deassert(tegra->reset); + return err; + } + + err = clk_prepare_enable(tegra->clock_tsensor); + if (err) { + clk_disable_unprepare(tegra->clock_soctherm); + reset_control_deassert(tegra->reset); + return err; + } + } else { + clk_disable_unprepare(tegra->clock_tsensor); + clk_disable_unprepare(tegra->clock_soctherm); + } + + reset_control_deassert(tegra->reset); + + return 0; +} + static const struct of_device_id tegra_soctherm_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_124_SOC { @@ -496,20 +529,10 @@ static int tegra_soctherm_probe(struct platform_device *pdev) return PTR_ERR(tegra->clock_soctherm); } - reset_control_assert(tegra->reset); - - err = clk_prepare_enable(tegra->clock_soctherm); + err = soctherm_clk_enable(pdev, true); if (err) return err; - err = clk_prepare_enable(tegra->clock_tsensor); - if (err) { - clk_disable_unprepare(tegra->clock_soctherm); - return err; - } - - reset_control_deassert(tegra->reset); - /* Initialize raw sensors */ tegra->calib = devm_kzalloc(&pdev->dev, @@ -579,8 +602,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev) return 0; disable_clocks: - clk_disable_unprepare(tegra->clock_tsensor); - clk_disable_unprepare(tegra->clock_soctherm); + soctherm_clk_enable(pdev, false); return err; } @@ -591,8 +613,7 @@ static int tegra_soctherm_remove(struct platform_device *pdev) debugfs_remove_recursive(tegra->debugfs_dir); - clk_disable_unprepare(tegra->clock_tsensor); - clk_disable_unprepare(tegra->clock_soctherm); + soctherm_clk_enable(pdev, false); return 0; }