From patchwork Wed Mar 16 08:58:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 8596851 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 780BAC0553 for ; Wed, 16 Mar 2016 09:00:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 74EA32034B for ; Wed, 16 Mar 2016 09:00:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 57E7E20304 for ; Wed, 16 Mar 2016 09:00:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965930AbcCPI6a (ORCPT ); Wed, 16 Mar 2016 04:58:30 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5781 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933898AbcCPI60 (ORCPT ); Wed, 16 Mar 2016 04:58:26 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 16 Mar 2016 01:58:21 -0700 Received: from HQMAIL107.nvidia.com ([172.20.187.13]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 16 Mar 2016 01:57:37 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 16 Mar 2016 01:57:37 -0700 Received: from HKMAIL101.nvidia.com (10.18.16.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 16 Mar 2016 08:58:24 +0000 Received: from niwei-dev.nvidia.com (10.19.224.146) by HKMAIL101.nvidia.com (10.18.16.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 16 Mar 2016 08:58:21 +0000 From: Wei Ni To: , , CC: , , , , , , Wei Ni Subject: [PATCH V8 11/14] thermal: tegra: handle HW initialization in one funcotion Date: Wed, 16 Mar 2016 16:58:35 +0800 Message-ID: <1458118715-30036-1-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.19.224.146] X-ClientProxiedBy: HKMAIL101.nvidia.com (10.18.16.10) To HKMAIL101.nvidia.com (10.18.16.10) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Handle HW initialization in one function soctherm_init(), so that the codes are more clear. Signed-off-by: Wei Ni --- drivers/thermal/tegra/soctherm.c | 85 +++++++++++++++++++++------------------- 1 file changed, 44 insertions(+), 41 deletions(-) diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c index f60106884ac4..52793132bd4e 100644 --- a/drivers/thermal/tegra/soctherm.c +++ b/drivers/thermal/tegra/soctherm.c @@ -95,19 +95,11 @@ struct tegra_soctherm { struct dentry *debugfs_dir; }; -static int enable_tsensor(struct tegra_soctherm *tegra, - unsigned int i, - const struct tsensor_shared_calib *shared) +static void enable_tsensor(struct tegra_soctherm *tegra, unsigned int i) { const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i]; void __iomem *base = tegra->regs + sensor->base; - u32 *calib = &tegra->calib[i]; unsigned int val; - int err; - - err = tegra_calc_tsensor_calib(sensor, shared, calib); - if (err) - return err; val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT; writel(val, base + SENSOR_CONFIG0); @@ -118,9 +110,7 @@ static int enable_tsensor(struct tegra_soctherm *tegra, val |= SENSOR_CONFIG1_TEMP_ENABLE; writel(val, base + SENSOR_CONFIG1); - writel(*calib, base + SENSOR_CONFIG2); - - return 0; + writel(tegra->calib[i], base + SENSOR_CONFIG2); } /* @@ -461,6 +451,34 @@ static int soctherm_clk_enable(struct platform_device *pdev, bool enable) return 0; } +static void soctherm_init(struct platform_device *pdev) +{ + struct tegra_soctherm *tegra = platform_get_drvdata(pdev); + const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs; + int i; + u32 pdiv, hotspot; + + /* Initialize raw sensors */ + for (i = 0; i < tegra->soc->num_tsensors; ++i) + enable_tsensor(tegra, i); + + /* program pdiv and hotspot offsets per THERM */ + pdiv = readl(tegra->regs + SENSOR_PDIV); + hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF); + for (i = 0; i < tegra->soc->num_ttgs; ++i) { + pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask, + ttgs[i]->pdiv); + /* hotspot offset from PLLX, doesn't need to configure PLLX */ + if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX) + continue; + hotspot = REG_SET_MASK(hotspot, + ttgs[i]->pllx_hotspot_mask, + ttgs[i]->pllx_hotspot_diff); + } + writel(pdiv, tegra->regs + SENSOR_PDIV); + writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF); +} + static const struct of_device_id tegra_soctherm_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_124_SOC { @@ -488,7 +506,6 @@ static int tegra_soctherm_probe(struct platform_device *pdev) struct tegra_soctherm_soc *soc; unsigned int i; int err; - u32 pdiv, hotspot; match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node); if (!match) @@ -529,45 +546,31 @@ static int tegra_soctherm_probe(struct platform_device *pdev) return PTR_ERR(tegra->clock_soctherm); } - err = soctherm_clk_enable(pdev, true); - if (err) - return err; - - /* Initialize raw sensors */ - tegra->calib = devm_kzalloc(&pdev->dev, sizeof(u32) * soc->num_tsensors, GFP_KERNEL); - if (!tegra->calib) { - err = -ENOMEM; - goto disable_clocks; - } + if (!tegra->calib) + return -ENOMEM; + /* calculate shared calibration data */ err = tegra_calc_shared_calib(soc->tfuse, &shared_calib); if (err) - goto disable_clocks; + return err; + /* calculate tsensor calibaration data */ for (i = 0; i < soc->num_tsensors; ++i) { - err = enable_tsensor(tegra, i, &shared_calib); + err = tegra_calc_tsensor_calib(&soc->tsensors[i], + &shared_calib, + &tegra->calib[i]); if (err) - goto disable_clocks; + return err; } - /* Program pdiv and hotspot offsets per THERM */ - pdiv = readl(tegra->regs + SENSOR_PDIV); - hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF); - for (i = 0; i < soc->num_ttgs; ++i) { - pdiv = REG_SET_MASK(pdiv, soc->ttgs[i]->pdiv_mask, - soc->ttgs[i]->pdiv); - /* hotspot offset from PLLX, doesn't need to configure PLLX */ - if (soc->ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX) - continue; - hotspot = REG_SET_MASK(hotspot, - soc->ttgs[i]->pllx_hotspot_mask, - soc->ttgs[i]->pllx_hotspot_diff); - } - writel(pdiv, tegra->regs + SENSOR_PDIV); - writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF); + err = soctherm_clk_enable(pdev, true); + if (err) + return err; + + soctherm_init(pdev); for (i = 0; i < soc->num_ttgs; ++i) { struct tegra_thermctl_zone *zone =