From patchwork Tue Mar 29 09:18:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 8684341 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F00C09F44D for ; Tue, 29 Mar 2016 09:19:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2869F2026F for ; Tue, 29 Mar 2016 09:19:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 411C520253 for ; Tue, 29 Mar 2016 09:19:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756437AbcC2JR4 (ORCPT ); Tue, 29 Mar 2016 05:17:56 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:24817 "EHLO hkmmgate101.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755304AbcC2JRw (ORCPT ); Tue, 29 Mar 2016 05:17:52 -0400 Received: from hkpgpgate101.nvidia.com (Not Verified[10.18.92.9]) by hkmmgate101.nvidia.com id ; Tue, 29 Mar 2016 17:19:13 +0800 Received: from HKMAIL101.nvidia.com ([10.18.67.137]) by hkpgpgate101.nvidia.com (PGP Universal service); Tue, 29 Mar 2016 02:17:50 -0700 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Tue, 29 Mar 2016 02:17:50 -0700 Received: from niwei-dev.nvidia.com (10.19.224.146) by HKMAIL101.nvidia.com (10.18.16.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Tue, 29 Mar 2016 09:17:47 +0000 From: Wei Ni To: , , CC: , , , , , , Wei Ni Subject: [PATCH V9 10/14] thermal: tegra: handle clocks in one function Date: Tue, 29 Mar 2016 17:18:13 +0800 Message-ID: <1459243093-25554-1-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.19.224.146] X-ClientProxiedBy: DRBGMAIL102.nvidia.com (10.18.16.21) To HKMAIL101.nvidia.com (10.18.16.10) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Handle clock enable/disable codes in one function soctherm_clk_enable(), so that the codes are more clear. Signed-off-by: Wei Ni --- drivers/thermal/tegra/soctherm.c | 51 ++++++++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c index 365b45213327..deeb3b7e4dac 100644 --- a/drivers/thermal/tegra/soctherm.c +++ b/drivers/thermal/tegra/soctherm.c @@ -428,6 +428,39 @@ static void soctherm_debug_init(struct platform_device *pdev) static inline void soctherm_debug_init(struct platform_device *pdev) {} #endif +static int soctherm_clk_enable(struct platform_device *pdev, bool enable) +{ + struct tegra_soctherm *tegra = platform_get_drvdata(pdev); + int err; + + if (!tegra->clock_soctherm || !tegra->clock_tsensor) + return -EINVAL; + + reset_control_assert(tegra->reset); + + if (enable) { + err = clk_prepare_enable(tegra->clock_soctherm); + if (err) { + reset_control_deassert(tegra->reset); + return err; + } + + err = clk_prepare_enable(tegra->clock_tsensor); + if (err) { + clk_disable_unprepare(tegra->clock_soctherm); + reset_control_deassert(tegra->reset); + return err; + } + } else { + clk_disable_unprepare(tegra->clock_tsensor); + clk_disable_unprepare(tegra->clock_soctherm); + } + + reset_control_deassert(tegra->reset); + + return 0; +} + static const struct of_device_id tegra_soctherm_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_124_SOC { @@ -496,20 +529,10 @@ static int tegra_soctherm_probe(struct platform_device *pdev) return PTR_ERR(tegra->clock_soctherm); } - reset_control_assert(tegra->reset); - - err = clk_prepare_enable(tegra->clock_soctherm); + err = soctherm_clk_enable(pdev, true); if (err) return err; - err = clk_prepare_enable(tegra->clock_tsensor); - if (err) { - clk_disable_unprepare(tegra->clock_soctherm); - return err; - } - - reset_control_deassert(tegra->reset); - /* Initialize raw sensors */ tegra->calib = devm_kzalloc(&pdev->dev, @@ -579,8 +602,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev) return 0; disable_clocks: - clk_disable_unprepare(tegra->clock_tsensor); - clk_disable_unprepare(tegra->clock_soctherm); + soctherm_clk_enable(pdev, false); return err; } @@ -591,8 +613,7 @@ static int tegra_soctherm_remove(struct platform_device *pdev) debugfs_remove_recursive(tegra->debugfs_dir); - clk_disable_unprepare(tegra->clock_tsensor); - clk_disable_unprepare(tegra->clock_soctherm); + soctherm_clk_enable(pdev, false); return 0; }