From patchwork Tue Mar 29 09:18:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 8684271 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 05A379F44D for ; Tue, 29 Mar 2016 09:18:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1C827201F5 for ; Tue, 29 Mar 2016 09:18:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 81EC520220 for ; Tue, 29 Mar 2016 09:18:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756151AbcC2JSS (ORCPT ); Tue, 29 Mar 2016 05:18:18 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:27376 "EHLO hkmmgate102.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752040AbcC2JSQ (ORCPT ); Tue, 29 Mar 2016 05:18:16 -0400 Received: from hkpgpgate101.nvidia.com (Not Verified[10.18.92.9]) by hkmmgate102.nvidia.com id ; Tue, 29 Mar 2016 17:18:17 +0800 Received: from HKMAIL101.nvidia.com ([10.18.67.137]) by hkpgpgate101.nvidia.com (PGP Universal service); Tue, 29 Mar 2016 02:18:13 -0700 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Tue, 29 Mar 2016 02:18:13 -0700 Received: from niwei-dev.nvidia.com (10.19.224.146) by HKMAIL101.nvidia.com (10.18.16.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Tue, 29 Mar 2016 09:18:11 +0000 From: Wei Ni To: , , CC: , , , , , , Wei Ni Subject: [PATCH V9 12/14] thermal: tegra: add PM support Date: Tue, 29 Mar 2016 17:18:36 +0800 Message-ID: <1459243116-25676-1-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.19.224.146] X-ClientProxiedBy: HKMAIL101.nvidia.com (10.18.16.10) To HKMAIL101.nvidia.com (10.18.16.10) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add suspend/resume function in soctherm driver. Signed-off-by: Wei Ni --- drivers/thermal/tegra/soctherm.c | 46 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c index d2b7c255d71f..559c74279eb8 100644 --- a/drivers/thermal/tegra/soctherm.c +++ b/drivers/thermal/tegra/soctherm.c @@ -88,6 +88,7 @@ struct tegra_soctherm { struct clk *clock_tsensor; struct clk *clock_soctherm; void __iomem *regs; + struct thermal_zone_device **thermctl_tzs; u32 *calib; struct tegra_soctherm_soc *soc; @@ -566,6 +567,12 @@ static int tegra_soctherm_probe(struct platform_device *pdev) return err; } + tegra->thermctl_tzs = devm_kzalloc(&pdev->dev, + sizeof(*z) * soc->num_ttgs, + GFP_KERNEL); + if (!tegra->thermctl_tzs) + return -ENOMEM; + err = soctherm_clk_enable(pdev, true); if (err) return err; @@ -595,6 +602,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev) } zone->tz = z; + tegra->thermctl_tzs[soc->ttgs[i]->id] = z; /* Configure hw trip points */ tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z); @@ -621,11 +629,49 @@ static int tegra_soctherm_remove(struct platform_device *pdev) return 0; } +static int soctherm_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + + soctherm_clk_enable(pdev, false); + + return 0; +} + +static int soctherm_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct tegra_soctherm *tegra = platform_get_drvdata(pdev); + struct tegra_soctherm_soc *soc = tegra->soc; + int err, i; + + err = soctherm_clk_enable(pdev, true); + if (err) { + dev_err(&pdev->dev, + "Resume failed: enable clocks failed\n"); + return err; + } + + soctherm_init(pdev); + + for (i = 0; i < soc->num_ttgs; ++i) { + struct thermal_zone_device *tz; + + tz = tegra->thermctl_tzs[soc->ttgs[i]->id]; + tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz); + } + + return 0; +} + +static SIMPLE_DEV_PM_OPS(tegra_soctherm_pm, soctherm_suspend, soctherm_resume); + static struct platform_driver tegra_soctherm_driver = { .probe = tegra_soctherm_probe, .remove = tegra_soctherm_remove, .driver = { .name = "tegra_soctherm", + .pm = &tegra_soctherm_pm, .of_match_table = tegra_soctherm_of_match, }, };