From patchwork Tue May 3 09:32:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 9001751 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C347CBF29F for ; Tue, 3 May 2016 10:07:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DE75320270 for ; Tue, 3 May 2016 10:07:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F1B9120123 for ; Tue, 3 May 2016 10:07:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755621AbcECKHo (ORCPT ); Tue, 3 May 2016 06:07:44 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:4661 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750952AbcECKHn (ORCPT ); Tue, 3 May 2016 06:07:43 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 03 May 2016 03:07:14 -0700 Received: from HQMAIL101.nvidia.com ([172.20.187.10]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 03 May 2016 03:07:07 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 03 May 2016 03:07:07 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Tue, 3 May 2016 10:07:41 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Tue, 3 May 2016 10:07:41 +0000 Received: from niwei-dev.nvidia.com (Not Verified[10.19.224.146]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 03 May 2016 03:07:41 -0700 From: Wei Ni To: , , , CC: , , , , , , , Wei Ni Subject: [PATCH] arm64: tegra: fix compatible string for Tegra132 fuse node Date: Tue, 3 May 2016 17:32:22 +0800 Message-ID: <1462267942-2165-1-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch changes the compatible of Tegra132 fuse node to "nvidia,tegra132-efuse", instead of "nvidia,tegra1124-efuse". Because the CONFIG_ARCH_TEGRA_124_SOC will not be enabled for Tegra132, the fuse driver can't find the corresponding node. Signed-off-by: Wei Ni --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 5d013809448b..ee101cb52f70 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -582,7 +582,7 @@ }; fuse@7000f800 { - compatible = "nvidia,tegra124-efuse"; + compatible = "nvidia,tegra132-efuse"; reg = <0x0 0x7000f800 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_FUSE>; clock-names = "fuse";