From patchwork Wed May 11 10:20:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 9067351 X-Patchwork-Delegate: rui.zhang@intel.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8C8BFBF29F for ; Wed, 11 May 2016 10:20:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0BC2B201BC for ; Wed, 11 May 2016 10:20:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 249D520145 for ; Wed, 11 May 2016 10:20:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932160AbcEKKTJ (ORCPT ); Wed, 11 May 2016 06:19:09 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5023 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932153AbcEKKTG (ORCPT ); Wed, 11 May 2016 06:19:06 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 11 May 2016 03:18:07 -0700 Received: from HQHUB101.nvidia.com ([172.20.187.24]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 11 May 2016 03:18:08 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 11 May 2016 03:18:08 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQHUB101.nvidia.com (172.20.187.24) with Microsoft SMTP Server (TLS) id 8.3.406.0; Wed, 11 May 2016 03:19:00 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 11 May 2016 10:19:00 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 11 May 2016 10:19:00 +0000 Received: from niwei-dev.nvidia.com (Not Verified[10.19.224.146]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,5,8150) id ; Wed, 11 May 2016 03:19:00 -0700 From: Wei Ni To: , , , CC: , , , , , , , Wei Ni Subject: [PATCH v5 06/11] arm64: tegra: use tegra132-soctherm for Tegra132 Date: Wed, 11 May 2016 18:20:21 +0800 Message-ID: <1462962026-19653-7-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462962026-19653-1-git-send-email-wni@nvidia.com> References: <1462962026-19653-1-git-send-email-wni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Tegra132 has the specific settings for soctherm, so change to use campatible "nvidia,tegra132-soctherm" for it. And adds cpu, gpu, mem and pllx thermal zones. Signed-off-by: Wei Ni --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 36 ++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 2013f8916084..e41d8e82d7ed 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra132", "nvidia,tegra124"; @@ -727,8 +728,8 @@ }; soctherm: thermal-sensor@700e2000 { - compatible = "nvidia,tegra124-soctherm"; - reg = <0x0 0x700e2000 0x0 0x1000>; + compatible = "nvidia,tegra132-soctherm"; + reg = <0x0 0x700e2000 0x0 0x600>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, <&tegra_car TEGRA124_CLK_SOC_THERM>; @@ -738,6 +739,37 @@ #thermal-sensor-cells = <1>; }; + thermal-zones { + cpu { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + }; + mem { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + }; + gpu { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + }; + pllx { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + }; + }; + ahub@70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>,